# RUN: llc -O0 -mtriple arm-- -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
  define void @test_icmp_eq_s32() { ret void }
  define void @test_icmp_ne_s32() { ret void }
  define void @test_icmp_ugt_s32() { ret void }
  define void @test_icmp_uge_s32() { ret void }
  define void @test_icmp_ult_s32() { ret void }
  define void @test_icmp_ule_s32() { ret void }
  define void @test_icmp_sgt_s32() { ret void }
  define void @test_icmp_sge_s32() { ret void }
  define void @test_icmp_slt_s32() { ret void }
  define void @test_icmp_sle_s32() { ret void }

  define void @test_fcmp_true_s32() #0 { ret void }
  define void @test_fcmp_false_s32() #0 { ret void }

  define void @test_fcmp_oeq_s32() #0 { ret void }
  define void @test_fcmp_ogt_s32() #0 { ret void }
  define void @test_fcmp_oge_s32() #0 { ret void }
  define void @test_fcmp_olt_s32() #0 { ret void }
  define void @test_fcmp_ole_s32() #0 { ret void }
  define void @test_fcmp_ord_s32() #0 { ret void }
  define void @test_fcmp_ugt_s32() #0 { ret void }
  define void @test_fcmp_uge_s32() #0 { ret void }
  define void @test_fcmp_ult_s32() #0 { ret void }
  define void @test_fcmp_ule_s32() #0 { ret void }
  define void @test_fcmp_une_s32() #0 { ret void }
  define void @test_fcmp_uno_s32() #0 { ret void }

  define void @test_fcmp_one_s32() #0 { ret void }
  define void @test_fcmp_ueq_s32() #0 { ret void }

  attributes #0 = { "target-features"="+vfp2" }
...
---
name:            test_icmp_eq_s32
# CHECK-LABEL: name: test_icmp_eq_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0

    %1(s32) = COPY %r1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1

    %2(s1) = G_ICMP intpred(eq),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_icmp_ne_s32
# CHECK-LABEL: name: test_icmp_ne_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0

    %1(s32) = COPY %r1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1

    %2(s1) = G_ICMP intpred(ne),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 1, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_icmp_ugt_s32
# CHECK-LABEL: name: test_icmp_ugt_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0

    %1(s32) = COPY %r1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1

    %2(s1) = G_ICMP intpred(ugt),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 8, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_icmp_uge_s32
# CHECK-LABEL: name: test_icmp_uge_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0

    %1(s32) = COPY %r1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1

    %2(s1) = G_ICMP intpred(uge),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 2, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_icmp_ult_s32
# CHECK-LABEL: name: test_icmp_ult_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0

    %1(s32) = COPY %r1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1

    %2(s1) = G_ICMP intpred(ult),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 3, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_icmp_ule_s32
# CHECK-LABEL: name: test_icmp_ule_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0

    %1(s32) = COPY %r1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1

    %2(s1) = G_ICMP intpred(ule),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 9, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_icmp_sgt_s32
# CHECK-LABEL: name: test_icmp_sgt_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0

    %1(s32) = COPY %r1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1

    %2(s1) = G_ICMP intpred(sgt),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_icmp_sge_s32
# CHECK-LABEL: name: test_icmp_sge_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0

    %1(s32) = COPY %r1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1

    %2(s1) = G_ICMP intpred(sge),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 10, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_icmp_slt_s32
# CHECK-LABEL: name: test_icmp_slt_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0

    %1(s32) = COPY %r1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1

    %2(s1) = G_ICMP intpred(slt),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 11, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_icmp_sle_s32
# CHECK-LABEL: name: test_icmp_sle_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0

    %1(s32) = COPY %r1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1

    %2(s1) = G_ICMP intpred(sle),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 13, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_true_s32
# CHECK-LABEL: name: test_fcmp_true_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: fprb }
  - { id: 1, class: fprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %s0, %s1

    %0(s32) = COPY %s0
    %1(s32) = COPY %s1

    %2(s1) = G_FCMP floatpred(true),  %0(s32), %1
    ; CHECK: [[RES:%[0-9]+]] = MOVi 1, 14, _, _

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_false_s32
# CHECK-LABEL: name: test_fcmp_false_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: fprb }
  - { id: 1, class: fprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %s0, %s1

    %0(s32) = COPY %s0
    %1(s32) = COPY %s1

    %2(s1) = G_FCMP floatpred(false),  %0(s32), %1
    ; CHECK: [[RES:%[0-9]+]] = MOVi 0, 14, _, _

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_oeq_s32
# CHECK-LABEL: name: test_fcmp_oeq_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: fprb }
  - { id: 1, class: fprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %s0, %s1

    %0(s32) = COPY %s0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0

    %1(s32) = COPY %s1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1

    %2(s1) = G_FCMP floatpred(oeq),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_ogt_s32
# CHECK-LABEL: name: test_fcmp_ogt_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: fprb }
  - { id: 1, class: fprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %s0, %s1

    %0(s32) = COPY %s0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0

    %1(s32) = COPY %s1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1

    %2(s1) = G_FCMP floatpred(ogt),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_oge_s32
# CHECK-LABEL: name: test_fcmp_oge_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: fprb }
  - { id: 1, class: fprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %s0, %s1

    %0(s32) = COPY %s0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0

    %1(s32) = COPY %s1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1

    %2(s1) = G_FCMP floatpred(oge),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 10, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_olt_s32
# CHECK-LABEL: name: test_fcmp_olt_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: fprb }
  - { id: 1, class: fprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %s0, %s1

    %0(s32) = COPY %s0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0

    %1(s32) = COPY %s1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1

    %2(s1) = G_FCMP floatpred(olt),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 4, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_ole_s32
# CHECK-LABEL: name: test_fcmp_ole_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: fprb }
  - { id: 1, class: fprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %s0, %s1

    %0(s32) = COPY %s0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0

    %1(s32) = COPY %s1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1

    %2(s1) = G_FCMP floatpred(ole),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 9, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_ord_s32
# CHECK-LABEL: name: test_fcmp_ord_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: fprb }
  - { id: 1, class: fprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %s0, %s1

    %0(s32) = COPY %s0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0

    %1(s32) = COPY %s1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1

    %2(s1) = G_FCMP floatpred(ord),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 7, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_ugt_s32
# CHECK-LABEL: name: test_fcmp_ugt_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: fprb }
  - { id: 1, class: fprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %s0, %s1

    %0(s32) = COPY %s0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0

    %1(s32) = COPY %s1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1

    %2(s1) = G_FCMP floatpred(ugt),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 8, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_uge_s32
# CHECK-LABEL: name: test_fcmp_uge_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: fprb }
  - { id: 1, class: fprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %s0, %s1

    %0(s32) = COPY %s0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0

    %1(s32) = COPY %s1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1

    %2(s1) = G_FCMP floatpred(uge),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 5, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_ult_s32
# CHECK-LABEL: name: test_fcmp_ult_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: fprb }
  - { id: 1, class: fprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %s0, %s1

    %0(s32) = COPY %s0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0

    %1(s32) = COPY %s1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1

    %2(s1) = G_FCMP floatpred(ult),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 11, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_ule_s32
# CHECK-LABEL: name: test_fcmp_ule_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: fprb }
  - { id: 1, class: fprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %s0, %s1

    %0(s32) = COPY %s0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0

    %1(s32) = COPY %s1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1

    %2(s1) = G_FCMP floatpred(ule),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 13, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_une_s32
# CHECK-LABEL: name: test_fcmp_une_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: fprb }
  - { id: 1, class: fprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %s0, %s1

    %0(s32) = COPY %s0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0

    %1(s32) = COPY %s1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1

    %2(s1) = G_FCMP floatpred(une),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 1, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_uno_s32
# CHECK-LABEL: name: test_fcmp_uno_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: fprb }
  - { id: 1, class: fprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %s0, %s1

    %0(s32) = COPY %s0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0

    %1(s32) = COPY %s1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1

    %2(s1) = G_FCMP floatpred(uno),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 6, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_one_s32
# CHECK-LABEL: name: test_fcmp_one_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: fprb }
  - { id: 1, class: fprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %s0, %s1

    %0(s32) = COPY %s0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0

    %1(s32) = COPY %s1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1

    %2(s1) = G_FCMP floatpred(one),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
    ; CHECK: [[RES1:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr
    ; CHECK: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[RES1]], 1, 4, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...
---
name:            test_fcmp_ueq_s32
# CHECK-LABEL: name: test_fcmp_ueq_s32
legalized:       true
regBankSelected: true
selected:        false
# CHECK: selected: true
registers:
  - { id: 0, class: fprb }
  - { id: 1, class: fprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
body:             |
  bb.0:
    liveins: %s0, %s1

    %0(s32) = COPY %s0
    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0

    %1(s32) = COPY %s1
    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1

    %2(s1) = G_FCMP floatpred(ueq),  %0(s32), %1
    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
    ; CHECK: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
    ; CHECK: [[RES1:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr
    ; CHECK: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
    ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[RES1]], 1, 6, %cpsr

    %3(s32) = G_ZEXT %2(s1)
    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _

    %r0 = COPY %3(s32)
    ; CHECK: %r0 = COPY [[RET]]

    BX_RET 14, _, implicit %r0
    ; CHECK: BX_RET 14, _, implicit %r0
...