; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -stop-after=irtranslator -global-isel %s -o - | FileCheck %s

; Check that we correctly skip over disabled inputs
define amdgpu_ps void @disabled_input(float inreg %arg0, float %psinput0, float %psinput1) #1 {
  ; CHECK-LABEL: name: disabled_input
  ; CHECK: bb.1.main_body:
  ; CHECK:   liveins: $sgpr2, $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; CHECK:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 0, 15, [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY1]](s32), 0, 0
  ; CHECK:   S_ENDPGM 0
main_body:
  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg0, float %arg0, float %arg0, float %psinput1, i1 false, i1 false) #0
  ret void
}

define amdgpu_ps void @disabled_input_struct(float inreg %arg0, { float, float } %psinput0, float %psinput1) #1 {
  ; CHECK-LABEL: name: disabled_input_struct
  ; CHECK: bb.1.main_body:
  ; CHECK:   liveins: $sgpr2, $vgpr0
  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; CHECK:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; CHECK:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; CHECK:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 0, 15, [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY1]](s32), 0, 0
  ; CHECK:   S_ENDPGM 0
main_body:
  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg0, float %arg0, float %arg0, float %psinput1, i1 false, i1 false) #0
  ret void
}

declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg)  #0

attributes #0 = { nounwind }
attributes #1 = { "InitialPSInputAddr"="0x00002" }