From f87d41d8b9f8cd8b1095dfe92c58ca4323720c0f Mon Sep 17 00:00:00 2001 From: Scott Michel Date: Mon, 5 Jan 2009 01:35:22 +0000 Subject: CellSPU: - Add an 8-bit operation test, which doesn't do much at this point. llvm-svn: 61665 --- llvm/test/CodeGen/CellSPU/i8ops.ll | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 llvm/test/CodeGen/CellSPU/i8ops.ll (limited to 'llvm') diff --git a/llvm/test/CodeGen/CellSPU/i8ops.ll b/llvm/test/CodeGen/CellSPU/i8ops.ll new file mode 100644 index 00000000000..23a036e3744 --- /dev/null +++ b/llvm/test/CodeGen/CellSPU/i8ops.ll @@ -0,0 +1,25 @@ +; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s + +; ModuleID = 'i8ops.bc' +target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" +target triple = "spu" + +define i8 @add_i8(i8 %a, i8 %b) nounwind { + %1 = add i8 %a, %b + ret i8 %1 +} + +define i8 @add_i8_imm(i8 %a, i8 %b) nounwind { + %1 = add i8 %a, 15 + ret i8 %1 +} + +define i8 @sub_i8(i8 %a, i8 %b) nounwind { + %1 = sub i8 %a, %b + ret i8 %1 +} + +define i8 @sub_i8_imm(i8 %a, i8 %b) nounwind { + %1 = sub i8 %a, 15 + ret i8 %1 +} -- cgit v1.2.3