From f3f3dd584a6b72572e96454f47a20c382c98b23c Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sun, 23 Sep 2018 21:19:15 +0000 Subject: [X86] Split WriteShift/WriteRotate schedule classes by CL usage. Variable Shifts/Rotates using the CL register have different behaviours to the immediate instructions - split accordingly to help remove yet more repeated overrides from the schedule models. llvm-svn: 342852 --- llvm/lib/Target/X86/X86InstrShiftRotate.td | 44 +++++++++++++++------------- llvm/lib/Target/X86/X86SchedBroadwell.td | 17 +++-------- llvm/lib/Target/X86/X86SchedHaswell.td | 17 +++-------- llvm/lib/Target/X86/X86SchedSandyBridge.td | 17 +++-------- llvm/lib/Target/X86/X86SchedSkylakeClient.td | 17 +++-------- llvm/lib/Target/X86/X86SchedSkylakeServer.td | 17 +++-------- llvm/lib/Target/X86/X86Schedule.td | 6 ++-- llvm/lib/Target/X86/X86ScheduleAtom.td | 6 ++-- llvm/lib/Target/X86/X86ScheduleBtVer2.td | 6 ++-- llvm/lib/Target/X86/X86ScheduleSLM.td | 6 ++-- llvm/lib/Target/X86/X86ScheduleZnver1.td | 6 ++-- 11 files changed, 64 insertions(+), 95 deletions(-) (limited to 'llvm') diff --git a/llvm/lib/Target/X86/X86InstrShiftRotate.td b/llvm/lib/Target/X86/X86InstrShiftRotate.td index 65be5b199db..e0bf47fd3fd 100644 --- a/llvm/lib/Target/X86/X86InstrShiftRotate.td +++ b/llvm/lib/Target/X86/X86InstrShiftRotate.td @@ -16,7 +16,7 @@ let Defs = [EFLAGS] in { let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in { -let Uses = [CL] in { +let Uses = [CL], SchedRW = [WriteShiftCL] in { def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1), "shl{b}\t{%cl, $dst|$dst, cl}", [(set GR8:$dst, (shl GR8:$src1, CL))]>; @@ -29,7 +29,7 @@ def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1), def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1), "shl{q}\t{%cl, $dst|$dst, cl}", [(set GR64:$dst, (shl GR64:$src1, CL))]>; -} // Uses = [CL] +} // Uses = [CL], SchedRW def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2), "shl{b}\t{$src2, $dst|$dst, $src2}", @@ -64,11 +64,9 @@ def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1), } // hasSideEffects = 0 } // Constraints = "$src = $dst", SchedRW - -let SchedRW = [WriteShiftLd, WriteRMW] in { // FIXME: Why do we need an explicit "Uses = [CL]" when the instr has a pattern // using CL? -let Uses = [CL] in { +let Uses = [CL], SchedRW = [WriteShiftCLLd, WriteRMW] in { def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst), "shl{b}\t{%cl, $dst|$dst, cl}", [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>; @@ -85,6 +83,8 @@ def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst), [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>, Requires<[In64BitMode]>; } + +let SchedRW = [WriteShiftLd, WriteRMW] in { def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, u8imm:$src), "shl{b}\t{$src, $dst|$dst, $src}", [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; @@ -120,7 +120,7 @@ def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst), } // SchedRW let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in { -let Uses = [CL] in { +let Uses = [CL], SchedRW = [WriteShiftCL] in { def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1), "shr{b}\t{%cl, $dst|$dst, cl}", [(set GR8:$dst, (srl GR8:$src1, CL))]>; @@ -166,8 +166,7 @@ def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1), } // Constraints = "$src = $dst", SchedRW -let SchedRW = [WriteShiftLd, WriteRMW] in { -let Uses = [CL] in { +let Uses = [CL], SchedRW = [WriteShiftCLLd, WriteRMW] in { def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst), "shr{b}\t{%cl, $dst|$dst, cl}", [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>; @@ -184,6 +183,8 @@ def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst), [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>, Requires<[In64BitMode]>; } + +let SchedRW = [WriteShiftLd, WriteRMW] in { def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, u8imm:$src), "shr{b}\t{$src, $dst|$dst, $src}", [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; @@ -219,7 +220,7 @@ def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst), } // SchedRW let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in { -let Uses = [CL] in { +let Uses = [CL], SchedRW = [WriteShiftCL] in { def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1), "sar{b}\t{%cl, $dst|$dst, cl}", [(set GR8:$dst, (sra GR8:$src1, CL))]>; @@ -268,8 +269,7 @@ def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1), } // Constraints = "$src = $dst", SchedRW -let SchedRW = [WriteShiftLd, WriteRMW] in { -let Uses = [CL] in { +let Uses = [CL], SchedRW = [WriteShiftCLLd, WriteRMW] in { def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst), "sar{b}\t{%cl, $dst|$dst, cl}", [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>; @@ -286,6 +286,8 @@ def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst), [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>, Requires<[In64BitMode]>; } + +let SchedRW = [WriteShiftLd, WriteRMW] in { def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, u8imm:$src), "sar{b}\t{$src, $dst|$dst, $src}", [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; @@ -327,7 +329,7 @@ def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst), let hasSideEffects = 0 in { let Constraints = "$src1 = $dst", SchedRW = [WriteRotate] in { -let Uses = [CL, EFLAGS] in { +let Uses = [CL, EFLAGS], SchedRW = [WriteRotateCL] in { def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1), "rcl{b}\t{%cl, $dst|$dst, cl}", []>; def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1), @@ -357,7 +359,7 @@ def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$cnt), "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>; } // Uses = [EFLAGS] -let Uses = [CL, EFLAGS] in { +let Uses = [CL, EFLAGS], SchedRW = [WriteRotateCL] in { def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1), "rcr{b}\t{%cl, $dst|$dst, cl}", []>; def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1), @@ -428,7 +430,7 @@ def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, u8imm:$cnt), Requires<[In64BitMode]>; } // Uses = [EFLAGS] -let Uses = [CL, EFLAGS] in { +let Uses = [CL, EFLAGS], SchedRW = [WriteRotateCLLd, WriteRMW] in { def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst), "rcl{b}\t{%cl, $dst|$dst, cl}", []>; def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst), @@ -454,7 +456,7 @@ def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst), let Constraints = "$src1 = $dst", SchedRW = [WriteRotate] in { // FIXME: provide shorter instructions when imm8 == 1 -let Uses = [CL] in { +let Uses = [CL], SchedRW = [WriteRotateCL] in { def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), "rol{b}\t{%cl, $dst|$dst, cl}", [(set GR8:$dst, (rotl GR8:$src1, CL))]>; @@ -498,8 +500,7 @@ def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1), [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>; } // Constraints = "$src = $dst", SchedRW -let SchedRW = [WriteRotateLd, WriteRMW] in { -let Uses = [CL] in { +let Uses = [CL], SchedRW = [WriteRotateCLLd, WriteRMW] in { def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst), "rol{b}\t{%cl, $dst|$dst, cl}", [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>; @@ -514,6 +515,8 @@ def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst), [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>, Requires<[In64BitMode]>; } + +let SchedRW = [WriteRotateLd, WriteRMW] in { def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, u8imm:$src1), "rol{b}\t{$src1, $dst|$dst, $src1}", [(store (rotl (loadi8 addr:$dst), (i8 imm:$src1)), addr:$dst)]>; @@ -549,7 +552,7 @@ def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst), } // SchedRW let Constraints = "$src1 = $dst", SchedRW = [WriteRotate] in { -let Uses = [CL] in { +let Uses = [CL], SchedRW = [WriteRotateCL] in { def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), "ror{b}\t{%cl, $dst|$dst, cl}", [(set GR8:$dst, (rotr GR8:$src1, CL))]>; @@ -595,8 +598,7 @@ def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1), [(set GR64:$dst, (rotl GR64:$src1, (i8 63)))]>; } // Constraints = "$src = $dst", SchedRW -let SchedRW = [WriteRotateLd, WriteRMW] in { -let Uses = [CL] in { +let Uses = [CL], SchedRW = [WriteRotateCLLd, WriteRMW] in { def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst), "ror{b}\t{%cl, $dst|$dst, cl}", [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>; @@ -611,6 +613,8 @@ def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst), [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>, Requires<[In64BitMode]>; } + +let SchedRW = [WriteRotateLd, WriteRMW] in { def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, u8imm:$src), "ror{b}\t{$src, $dst|$dst, $src}", [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td index 54104ed009c..2e91426ac04 100755 --- a/llvm/lib/Target/X86/X86SchedBroadwell.td +++ b/llvm/lib/Target/X86/X86SchedBroadwell.td @@ -150,8 +150,10 @@ defm : BWWriteResPair; defm : BWWriteResPair; // Integer shifts and rotates. -defm : BWWriteResPair; -defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; +defm : BWWriteResPair; // SHLD/SHRD. defm : X86WriteRes; @@ -772,17 +774,6 @@ def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> { def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r(1|i)", "RCR(8|16|32|64)r(1|i)")>; -def BWWriteResGroup36 : SchedWriteRes<[BWPort06,BWPort0156]> { - let Latency = 3; - let NumMicroOps = 3; - let ResourceCycles = [2,1]; -} -def: InstRW<[BWWriteResGroup36], (instregex "ROL(8|16|32|64)rCL", - "ROR(8|16|32|64)rCL", - "SAR(8|16|32|64)rCL", - "SHL(8|16|32|64)rCL", - "SHR(8|16|32|64)rCL")>; - def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> { let Latency = 3; let NumMicroOps = 4; diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index 2fe3e0e7a4d..f5d6334a0d6 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -133,8 +133,10 @@ defm : X86WriteRes; def : WriteRes { let Latency = 3; } // Integer shifts and rotates. -defm : HWWriteResPair; -defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; +defm : HWWriteResPair; // SHLD/SHRD. defm : X86WriteRes; @@ -1286,17 +1288,6 @@ def HWWriteResGroup59 : SchedWriteRes<[HWPort06,HWPort0156]> { def: InstRW<[HWWriteResGroup59], (instregex "RCL(8|16|32|64)r(1|i)", "RCR(8|16|32|64)r(1|i)")>; -def HWWriteResGroup60 : SchedWriteRes<[HWPort06,HWPort0156]> { - let Latency = 3; - let NumMicroOps = 3; - let ResourceCycles = [2,1]; -} -def: InstRW<[HWWriteResGroup60], (instregex "ROL(8|16|32|64)rCL", - "ROR(8|16|32|64)rCL", - "SAR(8|16|32|64)rCL", - "SHL(8|16|32|64)rCL", - "SHR(8|16|32|64)rCL")>; - def HWWriteResGroup61 : SchedWriteRes<[HWPort0,HWPort4,HWPort237]> { let Latency = 4; let NumMicroOps = 3; diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index 740a5565162..e9725b799a5 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -135,8 +135,10 @@ defm : X86WriteRes; defm : X86WriteRes; defm : X86WriteRes; -defm : SBWriteResPair; -defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; defm : SBWriteResPair; defm : SBWriteResPair; @@ -661,17 +663,6 @@ def SBWriteResGroup23 : SchedWriteRes<[SBPort05]> { def: InstRW<[SBWriteResGroup23], (instregex "RCL(8|16|32|64)r1", "RCR(8|16|32|64)r1")>; -def SBWriteResGroup23_2 : SchedWriteRes<[SBPort05]> { - let Latency = 3; - let NumMicroOps = 3; - let ResourceCycles = [3]; -} -def: InstRW<[SBWriteResGroup23_2], (instregex "ROL(8|16|32|64)rCL", - "ROR(8|16|32|64)rCL", - "SAR(8|16|32|64)rCL", - "SHL(8|16|32|64)rCL", - "SHR(8|16|32|64)rCL")>; - def SBWriteResGroup25_1 : SchedWriteRes<[SBPort23,SBPort015]> { let Latency = 7; let NumMicroOps = 3; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index 87b9daab334..5bad160440b 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -149,8 +149,10 @@ defm : SKLWriteResPair; defm : SKLWriteResPair; // Integer shifts and rotates. -defm : SKLWriteResPair; -defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; // SHLD/SHRD. defm : X86WriteRes; @@ -759,17 +761,6 @@ def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> { } def: InstRW<[SKLWriteResGroup32], (instrs FNSTSW16r)>; -def SKLWriteResGroup33 : SchedWriteRes<[SKLPort06]> { - let Latency = 3; - let NumMicroOps = 3; - let ResourceCycles = [3]; -} -def: InstRW<[SKLWriteResGroup33], (instregex "ROL(8|16|32|64)rCL", - "ROR(8|16|32|64)rCL", - "SAR(8|16|32|64)rCL", - "SHL(8|16|32|64)rCL", - "SHR(8|16|32|64)rCL")>; - def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> { let Latency = 3; let NumMicroOps = 3; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index f671650c843..02a537363ca 100755 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -142,8 +142,10 @@ def : WriteRes; def : WriteRes; // // Integer shifts and rotates. -defm : SKXWriteResPair; -defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // SHLD/SHRD. defm : X86WriteRes; @@ -822,17 +824,6 @@ def SKXWriteResGroup34 : SchedWriteRes<[SKXPort0,SKXPort0156]> { } def: InstRW<[SKXWriteResGroup34], (instrs FNSTSW16r)>; -def SKXWriteResGroup35 : SchedWriteRes<[SKXPort06]> { - let Latency = 3; - let NumMicroOps = 3; - let ResourceCycles = [3]; -} -def: InstRW<[SKXWriteResGroup35], (instregex "ROL(8|16|32|64)rCL", - "ROR(8|16|32|64)rCL", - "SAR(8|16|32|64)rCL", - "SHL(8|16|32|64)rCL", - "SHR(8|16|32|64)rCL")>; - def SKXWriteResGroup37 : SchedWriteRes<[SKXPort0,SKXPort5]> { let Latency = 3; let NumMicroOps = 3; diff --git a/llvm/lib/Target/X86/X86Schedule.td b/llvm/lib/Target/X86/X86Schedule.td index e43f7fc142f..344a94f878d 100644 --- a/llvm/lib/Target/X86/X86Schedule.td +++ b/llvm/lib/Target/X86/X86Schedule.td @@ -148,8 +148,10 @@ def WriteLAHFSAHF : SchedWrite; // Load/Store flags in AH. def WriteBitTest : SchedWrite; // Bit Test - TODO add memory folding support // Integer shifts and rotates. -defm WriteShift : X86SchedWritePair; -defm WriteRotate : X86SchedWritePair; +defm WriteShift : X86SchedWritePair; +defm WriteShiftCL : X86SchedWritePair; +defm WriteRotate : X86SchedWritePair; +defm WriteRotateCL : X86SchedWritePair; // Double shift instructions. def WriteSHDrri : SchedWrite; diff --git a/llvm/lib/Target/X86/X86ScheduleAtom.td b/llvm/lib/Target/X86/X86ScheduleAtom.td index cd6f22288d3..470ef1f069a 100644 --- a/llvm/lib/Target/X86/X86ScheduleAtom.td +++ b/llvm/lib/Target/X86/X86ScheduleAtom.td @@ -153,8 +153,10 @@ defm : X86WriteResPairUnsupported; // Integer shifts and rotates. //////////////////////////////////////////////////////////////////////////////// -defm : AtomWriteResPair; -defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; +defm : AtomWriteResPair; defm : X86WriteRes; defm : X86WriteRes; diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td index 5cc185657c3..d7fb6a32888 100644 --- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td +++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td @@ -212,8 +212,10 @@ defm : X86WriteResPairUnsupported; // Integer shifts and rotates. //////////////////////////////////////////////////////////////////////////////// -defm : JWriteResIntPair; -defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; +defm : JWriteResIntPair; // SHLD/SHRD. defm : X86WriteRes; diff --git a/llvm/lib/Target/X86/X86ScheduleSLM.td b/llvm/lib/Target/X86/X86ScheduleSLM.td index 0fb4e69fd6d..2ed7a8d7ee0 100644 --- a/llvm/lib/Target/X86/X86ScheduleSLM.td +++ b/llvm/lib/Target/X86/X86ScheduleSLM.td @@ -104,8 +104,10 @@ defm : X86WriteRes; defm : X86WriteRes; defm : X86WriteRes; -defm : SLMWriteResPair; -defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; +defm : SLMWriteResPair; defm : X86WriteRes; defm : X86WriteRes; diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index 32f84b3623f..4539d0159b6 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -186,8 +186,10 @@ defm : X86WriteRes; defm : X86WriteRes; defm : X86WriteRes; -defm : ZnWriteResPair; -defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; +defm : ZnWriteResPair; defm : X86WriteRes; defm : X86WriteResUnsupported; -- cgit v1.2.3