From 7e1f66d6f5d679632b279b64bb1a0f338104730c Mon Sep 17 00:00:00 2001 From: Quentin Colombet Date: Thu, 22 Dec 2016 21:56:26 +0000 Subject: [RegisterBankInfo] Allow to set a register class when nothing else is set This is going to be needed to be able to constraint register class on target specific instruction while the RegBankSelect pass did not run yet. llvm-svn: 290375 --- llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'llvm') diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp index 34ec509b8ac..a6c93bc0f3d 100644 --- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp +++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp @@ -224,12 +224,11 @@ const TargetRegisterClass *RegisterBankInfo::constrainGenericRegister( return MRI.constrainRegClass(Reg, &RC); const RegisterBank *RB = RegClassOrBank.get(); - assert(RB && "Generic register does not have a register bank"); - // Otherwise, all we can do is ensure the bank covers the class, and set it. - if (!RB->covers(RC)) + if (RB && !RB->covers(RC)) return nullptr; + // If nothing was set or the class is simply compatible, set it. MRI.setRegClass(Reg, &RC); return &RC; } -- cgit v1.2.3