From 26a701f24f5e8ff0c2c2d0692148ee702b31d63f Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 23 Jan 2018 05:36:53 +0000 Subject: [X86] Various vXi1 insertion improvements. Add missing patterns for inserting v1i1 into a zero vector. Use insert_subvector to zero upper bits before inserting an element into a vXi1 vector. Replace kshift based isel pattern with insert_subvector based pattern now that code that caused the pattern has been fixed to emit insert_subvector. llvm-svn: 323173 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 10 +++++----- llvm/lib/Target/X86/X86InstrAVX512.td | 17 +++++------------ llvm/lib/Target/X86/X86InstrVecCompiler.td | 17 +++++++++++++++++ 3 files changed, 27 insertions(+), 17 deletions(-) (limited to 'llvm') diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index ad0eebf8b28..79bcde817ea 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -14920,12 +14920,12 @@ static SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG, } // Insertion of one bit into first position - if (IdxVal == 0 ) { + if (IdxVal == 0) { // Clean top bits of vector. - EltInVec = DAG.getNode(X86ISD::KSHIFTL, dl, VecVT, EltInVec, - DAG.getConstant(NumElems - 1, dl, MVT::i8)); - EltInVec = DAG.getNode(X86ISD::KSHIFTR, dl, VecVT, EltInVec, - DAG.getConstant(NumElems - 1, dl, MVT::i8)); + EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i1, Elt); + EltInVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VecVT, + getZeroVector(VecVT, Subtarget, DAG, dl), + EltInVec, DAG.getIntPtrConstant(0, dl)); // Clean the first bit in source vector. Vec = DAG.getNode(X86ISD::KSHIFTR, dl, VecVT, Vec, DAG.getConstant(1 , dl, MVT::i8)); diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 7f267e7f687..d9326372147 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -2761,19 +2761,12 @@ let Predicates = [HasAVX512] in { defm : operation_gpr_mask_copy_lowering; defm : operation_gpr_mask_copy_lowering; - def : Pat<(X86kshiftr (X86kshiftl (v1i1 (scalar_to_vector GR8:$src)), (i8 15)), (i8 15)) , - (COPY_TO_REGCLASS - (KMOVWkr (AND32ri8 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), - GR8:$src, sub_8bit), (i32 1))), VK1)>; - def : Pat<(X86kshiftr (X86kshiftl (v16i1 (scalar_to_vector GR8:$src)), (i8 15)), (i8 15)) , + def : Pat<(insert_subvector (v16i1 immAllZerosV), + (v1i1 (scalar_to_vector GR8:$src)), (iPTR 0)), (COPY_TO_REGCLASS - (KMOVWkr (AND32ri8 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), - GR8:$src, sub_8bit), (i32 1))), VK16)>; - def : Pat<(X86kshiftr (X86kshiftl (v8i1 (scalar_to_vector GR8:$src)), (i8 15)), (i8 15)) , - (COPY_TO_REGCLASS - (KMOVWkr (AND32ri8 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), - GR8:$src, sub_8bit), (i32 1))), VK8)>; - + (KMOVWkr (AND32ri8 + (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src, sub_8bit), + (i32 1))), VK16)>; } // Mask unary operation diff --git a/llvm/lib/Target/X86/X86InstrVecCompiler.td b/llvm/lib/Target/X86/X86InstrVecCompiler.td index b2ddfa89deb..1aef98ba49d 100644 --- a/llvm/lib/Target/X86/X86InstrVecCompiler.td +++ b/llvm/lib/Target/X86/X86InstrVecCompiler.td @@ -496,6 +496,11 @@ let Predicates = [HasBWI, HasVLX] in { // If the bits are not zero we have to fall back to explicitly zeroing by // using shifts. let Predicates = [HasAVX512] in { + def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), + (v1i1 VK1:$mask), (iPTR 0))), + (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK1:$mask, VK16), + (i8 15)), (i8 15))>; + def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), (v2i1 VK2:$mask), (iPTR 0))), (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK2:$mask, VK16), @@ -519,6 +524,10 @@ let Predicates = [HasDQI] in { (v8i1 VK8:$mask), (iPTR 0))), (COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK16)>; + def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), + (v1i1 VK1:$mask), (iPTR 0))), + (KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK1:$mask, VK8), + (i8 7)), (i8 7))>; def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), (v2i1 VK2:$mask), (iPTR 0))), (KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK2:$mask, VK8), @@ -565,6 +574,10 @@ let Predicates = [HasBWI, HasDQI] in { } let Predicates = [HasBWI, HasVLX] in { + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + (v1i1 VK1:$mask), (iPTR 0))), + (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK1:$mask, VK32), + (i8 31)), (i8 31))>; def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), (v2i1 VK2:$mask), (iPTR 0))), (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK2:$mask, VK32), @@ -574,6 +587,10 @@ let Predicates = [HasBWI, HasVLX] in { (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK4:$mask, VK32), (i8 28)), (i8 28))>; + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + (v1i1 VK1:$mask), (iPTR 0))), + (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK1:$mask, VK64), + (i8 63)), (i8 63))>; def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), (v2i1 VK2:$mask), (iPTR 0))), (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK2:$mask, VK64), -- cgit v1.2.3