From 1c315d54111faee947f5bd7ca3d4ffbeb89a003e Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Wed, 19 Dec 2012 22:10:34 +0000 Subject: R600: Remove unecessary VREG alignment. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Unlike SGPRs VGPRs doesn't need to be aligned. Patch by: Christian König Reviewed-by: Tom Stellard Tested-by: Michel Dänzer Signed-off-by: Christian König llvm-svn: 170593 --- llvm/lib/Target/R600/SIRegisterInfo.td | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'llvm') diff --git a/llvm/lib/Target/R600/SIRegisterInfo.td b/llvm/lib/Target/R600/SIRegisterInfo.td index e52311ab8a9..c3f136191a6 100644 --- a/llvm/lib/Target/R600/SIRegisterInfo.td +++ b/llvm/lib/Target/R600/SIRegisterInfo.td @@ -105,15 +105,15 @@ def VGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32, // VGPR 64-bit registers def VGPR_64 : RegisterTuples<[low, high], - [(add (decimate VGPR_32, 2)), - (add (decimate (rotl VGPR_32, 1), 2))]>; + [(add VGPR_32), + (add (rotl VGPR_32, 1))]>; // VGPR 128-bit registers def VGPR_128 : RegisterTuples<[sel_x, sel_y, sel_z, sel_w], - [(add (decimate VGPR_32, 4)), - (add (decimate (rotl VGPR_32, 1), 4)), - (add (decimate (rotl VGPR_32, 2), 4)), - (add (decimate (rotl VGPR_32, 3), 4))]>; + [(add VGPR_32), + (add (rotl VGPR_32, 1)), + (add (rotl VGPR_32, 2)), + (add (rotl VGPR_32, 3))]>; // Register class for all scalar registers (SGPRs + Special Registers) def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32, -- cgit v1.2.3