From abbc4a7f1aa056b316c40bbeafbf6b973f9c463d Mon Sep 17 00:00:00 2001 From: Matthias Braun Date: Mon, 28 Aug 2017 20:11:27 +0000 Subject: Address r311914 review comments llvm-svn: 311917 --- llvm/utils/TableGen/CodeGenRegisters.cpp | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'llvm/utils') diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp index 5ff1608afc9..425351ccf04 100644 --- a/llvm/utils/TableGen/CodeGenRegisters.cpp +++ b/llvm/utils/TableGen/CodeGenRegisters.cpp @@ -122,12 +122,11 @@ LaneBitmask CodeGenSubRegIndex::computeLaneMask() const { void CodeGenSubRegIndex::setConcatenationOf( ArrayRef Parts) { - if (ConcatenationOf.empty()) { + if (ConcatenationOf.empty()) ConcatenationOf.assign(Parts.begin(), Parts.end()); - } else { + else assert(std::equal(Parts.begin(), Parts.end(), ConcatenationOf.begin()) && "parts consistent"); - } } void CodeGenSubRegIndex::computeConcatTransitiveClosure() { @@ -492,16 +491,15 @@ void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) { SmallVector Parts; // We know that the first component is (SubRegIdx,SubReg). However we // may still need to split it into smaller subregister parts. - assert(Cand->ExplicitSubRegs[0] == SubReg); - assert(getSubRegIndex(SubReg) == SubRegIdx); + assert(Cand->ExplicitSubRegs[0] == SubReg && "LeadingSuperRegs correct"); + assert(getSubRegIndex(SubReg) == SubRegIdx && "LeadingSuperRegs correct"); for (CodeGenRegister *SubReg : Cand->ExplicitSubRegs) { if (CodeGenSubRegIndex *SubRegIdx = getSubRegIndex(SubReg)) { if (SubRegIdx->ConcatenationOf.empty()) { Parts.push_back(SubRegIdx); - } else { + } else for (CodeGenSubRegIndex *SubIdx : SubRegIdx->ConcatenationOf) Parts.push_back(SubIdx); - } } else { // Sub-register doesn't exist. Parts.clear(); -- cgit v1.2.3