From 331534e5bbd6593a7c3bc127aeaba83d2f6ea597 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Tue, 4 Oct 2011 15:28:44 +0000 Subject: TableGen: Store all allocation orders together. There is no need to keep the primary order separate. llvm-svn: 141082 --- llvm/utils/TableGen/CodeGenRegisters.h | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) (limited to 'llvm/utils/TableGen/CodeGenRegisters.h') diff --git a/llvm/utils/TableGen/CodeGenRegisters.h b/llvm/utils/TableGen/CodeGenRegisters.h index b8d2053cf9e..6e8d6c04e00 100644 --- a/llvm/utils/TableGen/CodeGenRegisters.h +++ b/llvm/utils/TableGen/CodeGenRegisters.h @@ -86,8 +86,8 @@ namespace llvm { class CodeGenRegisterClass { CodeGenRegister::Set Members; - const std::vector *Elements; - std::vector > AltOrders; + // Allocation orders. Order[0] always contains all registers in Members. + std::vector > Orders; // Bit mask of sub-classes including this, indexed by their EnumValue. BitVector SubClasses; // List of super-classes, topologocally ordered to have the larger classes @@ -154,14 +154,11 @@ namespace llvm { // The order of registers is the same as in the .td file. // No = 0 is the default allocation order, No = 1 is the first alternative. ArrayRef getOrder(unsigned No = 0) const { - if (No == 0) - return *Elements; - else - return AltOrders[No - 1]; + return Orders[No]; } // Return the total number of allocation orders available. - unsigned getNumOrders() const { return 1 + AltOrders.size(); } + unsigned getNumOrders() const { return Orders.size(); } // Get the set of registers. This set contains the same registers as // getOrder(0). -- cgit v1.2.3