From 13de555737e07b29d126ed72d8450f88bd38f66c Mon Sep 17 00:00:00 2001 From: Simon Dardis Date: Tue, 22 May 2018 14:36:58 +0000 Subject: [FastISel] Permit instructions to be skipped for FastISel generation. Some ISA's such as microMIPS32(R6) have instructions which are near identical for code generation purposes, e.g. xor and xor16. These instructions take the same value types for operands and return values, have the same instruction predicates and map to the same ISD opcode. (These instructions do differ by register classes.) In such cases, the FastISel generator rejects the instruction definition. This patch borrows the 'FastIselShouldIgnore' bit from rL129692 and enables applying it to an instruction definition. Reviewers: mcrosier Differential Revision: https://reviews.llvm.org/D46953 llvm-svn: 332983 --- llvm/utils/TableGen/CodeGenInstruction.cpp | 1 + 1 file changed, 1 insertion(+) (limited to 'llvm/utils/TableGen/CodeGenInstruction.cpp') diff --git a/llvm/utils/TableGen/CodeGenInstruction.cpp b/llvm/utils/TableGen/CodeGenInstruction.cpp index 44ee16f6fd7..bb6d9f0c707 100644 --- a/llvm/utils/TableGen/CodeGenInstruction.cpp +++ b/llvm/utils/TableGen/CodeGenInstruction.cpp @@ -327,6 +327,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R) isInsertSubreg = R->getValueAsBit("isInsertSubreg"); isConvergent = R->getValueAsBit("isConvergent"); hasNoSchedulingInfo = R->getValueAsBit("hasNoSchedulingInfo"); + FastISelShouldIgnore = R->getValueAsBit("FastISelShouldIgnore"); bool Unset; mayLoad = R->getValueAsBitOrUnset("mayLoad", Unset); -- cgit v1.2.3