From b36d428d27ba195e29bbb119e575a0a6d8261d33 Mon Sep 17 00:00:00 2001
From: Tim Northover <tnorthover@apple.com>
Date: Wed, 9 Apr 2014 07:07:02 +0000
Subject: ARM64: scalarize v1i64 mul operation

This is the second part of fixing PR19367.

llvm-svn: 205836
---
 llvm/test/CodeGen/ARM64/vmul.ll | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'llvm/test')

diff --git a/llvm/test/CodeGen/ARM64/vmul.ll b/llvm/test/CodeGen/ARM64/vmul.ll
index d11bb2f72eb..b6bd16ac0b4 100644
--- a/llvm/test/CodeGen/ARM64/vmul.ll
+++ b/llvm/test/CodeGen/ARM64/vmul.ll
@@ -2027,3 +2027,10 @@ define <16 x i8> @test_pmull_high_64(<2 x i64> %l, <2 x i64> %r) nounwind {
 }
 
 declare <16 x i8> @llvm.arm64.neon.pmull64(i64, i64)
+
+define <1 x i64> @test_mul_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) nounwind {
+; CHECK-LABEL: test_mul_v1i64:
+; CHECK: mul
+  %prod = mul <1 x i64> %lhs, %rhs
+  ret <1 x i64> %prod
+}
-- 
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