From ac450eb59e77deb929ea2ec9556b46fbf03a9698 Mon Sep 17 00:00:00 2001 From: Nadav Rotem Date: Thu, 6 Dec 2012 17:34:13 +0000 Subject: Fix a bug in the code that merges consecutive stores. Previously we did not check if loads that happen in between stores alias with the first store in the chain, only with the second store onwards. llvm-svn: 169516 --- .../CodeGen/X86/2012-12-06-python27-miscompile.ll | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 llvm/test/CodeGen/X86/2012-12-06-python27-miscompile.ll (limited to 'llvm/test') diff --git a/llvm/test/CodeGen/X86/2012-12-06-python27-miscompile.ll b/llvm/test/CodeGen/X86/2012-12-06-python27-miscompile.ll new file mode 100644 index 00000000000..d9effc92fa9 --- /dev/null +++ b/llvm/test/CodeGen/X86/2012-12-06-python27-miscompile.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -march=x86 -mcpu=corei7 -mtriple=i686-pc-win32 | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +; Make sure that we are zeroing one memory location at a time using xorl and +; not both using XMM registers. + +;CHECK: @foo +;CHECK: xorl +;CHECK-NOT: xmm +;CHECK: ret +define i32 @foo (i64* %so) nounwind uwtable ssp { +entry: + %used = getelementptr inbounds i64* %so, i32 3 + store i64 0, i64* %used, align 8 + %fill = getelementptr inbounds i64* %so, i32 2 + %L = load i64* %fill, align 8 + store i64 0, i64* %fill, align 8 + %cmp28 = icmp sgt i64 %L, 0 + %R = sext i1 %cmp28 to i32 + ret i32 %R +} -- cgit v1.2.3