From 7beb737b46e03d4b2b508df9ec2da93805fb5ef8 Mon Sep 17 00:00:00 2001 From: Zoran Jovanovic Date: Tue, 15 Sep 2015 10:05:10 +0000 Subject: [mips][microMIPS] Implement CACHEE and PREFE instructions for microMIPS32r6 Differential Revision: http://reviews.llvm.org/D11632 llvm-svn: 247670 --- llvm/test/MC/Disassembler/Mips/micromips32r6.txt | 4 ++++ llvm/test/MC/Mips/micromips32r6/valid.s | 2 ++ 2 files changed, 6 insertions(+) (limited to 'llvm/test') diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r6.txt b/llvm/test/MC/Disassembler/Mips/micromips32r6.txt index 9da4df60dc8..43debbe4acf 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips32r6.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips32r6.txt @@ -351,3 +351,7 @@ 0x25 0xe0 # CHECK: sll16 $3, $6, 8 0x25 0xe1 # CHECK: srl16 $3, $6, 8 + +0x60 0x25 0xa6 0x08 # CHECK: cachee 1, 8($5) + +0x60 0x25 0xa4 0x08 # CHECK: prefe 1, 8($5) diff --git a/llvm/test/MC/Mips/micromips32r6/valid.s b/llvm/test/MC/Mips/micromips32r6/valid.s index 0b4b3fe3e41..14f11427d59 100644 --- a/llvm/test/MC/Mips/micromips32r6/valid.s +++ b/llvm/test/MC/Mips/micromips32r6/valid.s @@ -179,4 +179,6 @@ or16 $3, $7 # CHECK: or16 $3, $7 # encoding: [0x45,0xf9] sll16 $3, $6, 8 # CHECK: sll16 $3, $6, 8 # encoding: [0x25,0xe0] srl16 $3, $6, 8 # CHECK: srl16 $3, $6, 8 # encoding: [0x25,0xe1] + prefe 1, 8($5) # CHECK: prefe 1, 8($5) # encoding: [0x60,0x25,0xa4,0x08] + cachee 1, 8($5) # CHECK: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08] -- cgit v1.2.3