From 779ba6d7b72bb52d6f46d273bed0ae45af075b12 Mon Sep 17 00:00:00 2001
From: Elena Demikhovsky <elena.demikhovsky@intel.com>
Date: Wed, 23 Nov 2011 10:23:16 +0000
Subject: I added several lines in X86 code generator that allow to choose
 VSHUFPS/VSHUFPD instructions while lowering VECTOR_SHUFFLE node. I check a
 commuted VSHUFP mask.

The patch was reviewed by Bruno.

llvm-svn: 145099
---
 llvm/test/CodeGen/X86/avx-vshufp.ll | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

(limited to 'llvm/test')

diff --git a/llvm/test/CodeGen/X86/avx-vshufp.ll b/llvm/test/CodeGen/X86/avx-vshufp.ll
index f06548dc3d6..7ec3a44e799 100644
--- a/llvm/test/CodeGen/X86/avx-vshufp.ll
+++ b/llvm/test/CodeGen/X86/avx-vshufp.ll
@@ -27,3 +27,17 @@ entry:
   %shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 undef>
   ret <4 x double> %shuffle
 }
+
+; CHECK: vshufps $-55, %ymm
+define <8 x float> @E(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp {
+entry:
+  %shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 9, i32 10, i32 0, i32 3, i32 13, i32 14, i32 4, i32 7>
+  ret <8 x float> %shuffle
+}
+
+; CHECK: vshufpd  $8, %ymm
+define <4 x double> @F(<4 x double> %a, <4 x double> %b) nounwind uwtable readnone ssp {
+entry:
+  %shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 7>
+  ret <4 x double> %shuffle
+}
-- 
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