From 5cc0e25324dc3984c89a5e0b57b29ce65d52ab1e Mon Sep 17 00:00:00 2001 From: Heejin Ahn Date: Fri, 29 Jun 2018 21:27:20 +0000 Subject: [WebAssembly] Update comments for non-splat pow2 vector test case Summary: After rL335727, (sdiv X, 1) is treated as a special case, so we can safely transform 'sdiv's in non-splat pow vectors into 'shr's even when some of its entries are '1'. The test expectations have been already fixed in rL335771, but the comments were out of date. Also changed the filename from `vector_sdiv.ll` to `vector-sdiv.ll` to be consistent with other test file names. Reviewers: RKSimon Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D48692 llvm-svn: 336018 --- llvm/test/CodeGen/WebAssembly/vector-sdiv.ll | 24 ++++++++++++++++++++++++ llvm/test/CodeGen/WebAssembly/vector_sdiv.ll | 22 ---------------------- 2 files changed, 24 insertions(+), 22 deletions(-) create mode 100644 llvm/test/CodeGen/WebAssembly/vector-sdiv.ll delete mode 100644 llvm/test/CodeGen/WebAssembly/vector_sdiv.ll (limited to 'llvm/test') diff --git a/llvm/test/CodeGen/WebAssembly/vector-sdiv.ll b/llvm/test/CodeGen/WebAssembly/vector-sdiv.ll new file mode 100644 index 00000000000..4aaf759caa5 --- /dev/null +++ b/llvm/test/CodeGen/WebAssembly/vector-sdiv.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s -asm-verbose=false -fast-isel=false -disable-wasm-fallthrough-return-opt | FileCheck %s + +target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" +target triple = "wasm32-unknown-unknown-elf" + +; This should be treated as a non-splat vector of pow2 divisor, so sdivs will be +; transformed to shrs in DAGCombiner. There will be 4 stores and 3 shrs (For '1' +; entry we don't need a shr). + +; CHECK-LABEL: vector_sdiv: +; CHECK-DAG: i32.store +; CHECK-DAG: i32.shr_u +; CHECK-DAG: i32.store +; CHECK-DAG: i32.shr_u +; CHECK-DAG: i32.store +; CHECK-DAG: i32.shr_u +; CHECK-DAG: i32.store +define void @vector_sdiv(<4 x i32>* %x, <4 x i32>* readonly %y) { +entry: + %0 = load <4 x i32>, <4 x i32>* %y, align 16 + %div = sdiv <4 x i32> %0, + store <4 x i32> %div, <4 x i32>* %x, align 16 + ret void +} diff --git a/llvm/test/CodeGen/WebAssembly/vector_sdiv.ll b/llvm/test/CodeGen/WebAssembly/vector_sdiv.ll deleted file mode 100644 index 142afbd1765..00000000000 --- a/llvm/test/CodeGen/WebAssembly/vector_sdiv.ll +++ /dev/null @@ -1,22 +0,0 @@ -; RUN: llc < %s -asm-verbose=false -fast-isel=false -disable-wasm-fallthrough-return-opt | FileCheck %s - -target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" -target triple = "wasm32-unknown-unknown-elf" - -; Because there is a 1 in the vector, sdiv should not be reduced to shifts. - -; CHECK-LABEL: vector_sdiv: -; CHECK-DAG: i32.store -; CHECK-DAG: i32.shr_u -; CHECK-DAG: i32.store -; CHECK-DAG: i32.shr_u -; CHECK-DAG: i32.store -; CHECK-DAG: i32.shr_u -; CHECK-DAG: i32.store -define void @vector_sdiv(<4 x i32>* %x, <4 x i32>* readonly %y) { -entry: - %0 = load <4 x i32>, <4 x i32>* %y, align 16 - %div = sdiv <4 x i32> %0, - store <4 x i32> %div, <4 x i32>* %x, align 16 - ret void -} -- cgit v1.2.3