From 53ce3f9d023e6688cdc3f2c687199d266c82f68c Mon Sep 17 00:00:00 2001 From: Marina Yatsina Date: Wed, 17 Aug 2016 19:07:40 +0000 Subject: Fix for PR29010 This is a fix for https://llvm.org/bugs/show_bug.cgi?id=29010 Root cause of the bug is that the register class of the machine instruction operand does not fully reflect if this registers that can be allocated. Both for i386 and x86_64 the operand's register class is VR128RegClass and thus contains xmm0-xmm15, though in i386 we can only use xmm0-xmm8. In order to get the actual allocable registers of the class we need to use RegisterClassInfo. Differential Revision: https://reviews.llvm.org/D23613 llvm-svn: 278954 --- llvm/test/CodeGen/X86/pr29010.ll | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 llvm/test/CodeGen/X86/pr29010.ll (limited to 'llvm/test') diff --git a/llvm/test/CodeGen/X86/pr29010.ll b/llvm/test/CodeGen/X86/pr29010.ll new file mode 100644 index 00000000000..a2d5ff69a35 --- /dev/null +++ b/llvm/test/CodeGen/X86/pr29010.ll @@ -0,0 +1,12 @@ +; RUN: llc < %s -mtriple=i386-linux -mattr=+avx | FileCheck %s + +; In i386 there are only 8 XMMs (xmm0-xmm7), make sure we we are not creating illegal XMM +define float @only_xmm0_7(i32 %arg) { +top: + tail call void asm sideeffect "", "~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{dirflag},~{fpsr},~{flags}"() + tail call void asm sideeffect "", "~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"() + %tmp1 = sitofp i32 %arg to float + ret float %tmp1 +;CHECK-LABEL:@only_xmm0_7 +;CHECK: vcvtsi2ssl {{.*}}, {{%xmm[0-7]+}}, {{%xmm[0-7]+}} +} -- cgit v1.2.3