From 4a50e68b65d6e4f0e7fceae1111e630726e2c12c Mon Sep 17 00:00:00 2001 From: Dale Johannesen Date: Tue, 18 Aug 2009 00:18:39 +0000 Subject: PowerPC inline asm was emitting two output operands for a single "m" constraint; this is wrong because the opcode of a load or store would have to change in parallel. This patch makes it always compute addresses into a register, which is correct but not as efficient as possible. 7144566. llvm-svn: 79292 --- .../2009-08-17-inline-asm-addr-mode-breakage.ll | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 llvm/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll (limited to 'llvm/test') diff --git a/llvm/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll b/llvm/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll new file mode 100644 index 00000000000..9e0c5de39f9 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll @@ -0,0 +1,22 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep add +; ModuleID = '' +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc-apple-darwin10.0" +; It is wrong on powerpc to substitute reg+reg for $0; the stw opcode +; would have to change. + +@x = external global [0 x i32] ; <[0 x i32]*> [#uses=1] + +define void @foo(i32 %y) nounwind ssp { +entry: + %y_addr = alloca i32 ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32 %y, i32* %y_addr + %0 = load i32* %y_addr, align 4 ; [#uses=1] + %1 = getelementptr inbounds [0 x i32]* @x, i32 0, i32 %0 ; [#uses=1] + call void asm sideeffect "isync\0A\09eieio\0A\09stw $1, $0", "=*o,r,~{memory}"(i32* %1, i32 0) nounwind + br label %return + +return: ; preds = %entry + ret void +} -- cgit v1.2.3