From 47fc44e52e8e7bad1b901bfae4dc78dec048d5f1 Mon Sep 17 00:00:00 2001
From: Elena Demikhovsky <elena.demikhovsky@intel.com>
Date: Mon, 16 Dec 2013 13:52:35 +0000
Subject: AVX-512: Added legal type MVT::i1 and VK1 register for it. Added
 scalar compare VCMPSS, VCMPSD. Implemented LowerSELECT for scalar FP
 operations. I replaced FSETCCss, FSETCCsd with one node type FSETCCs. Node
 extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1.

llvm-svn: 197384
---
 llvm/test/CodeGen/X86/avx512-insert-extract.ll | 22 ++++++++--------------
 llvm/test/CodeGen/X86/avx512-select.ll         | 19 +++++++++++++++++++
 llvm/test/CodeGen/X86/isint.ll                 |  4 ++--
 3 files changed, 29 insertions(+), 16 deletions(-)

(limited to 'llvm/test')

diff --git a/llvm/test/CodeGen/X86/avx512-insert-extract.ll b/llvm/test/CodeGen/X86/avx512-insert-extract.ll
index ef6359b4d9e..64f2a197008 100644
--- a/llvm/test/CodeGen/X86/avx512-insert-extract.ll
+++ b/llvm/test/CodeGen/X86/avx512-insert-extract.ll
@@ -99,27 +99,21 @@ define i32 @test10(<16 x i32> %x, i32 %ind) nounwind {
 }
 
 ;CHECK-LABEL: test11
-;CHECK: movl    $260
-;CHECK: bextrl
-;CHECK: movl    $268
-;CHECK: bextrl
+;CHECK: vpcmpltud
+;CKECK: kshiftlw $11
+;CKECK: kshiftrw $15
+;CHECK: kxorw
+;CHECK: kortestw
+;CHECK: jne
+;CHECK: ret
 ;CHECK: ret
 define <16 x i32> @test11(<16 x i32>%a, <16 x i32>%b) {
   %cmp_res = icmp ult <16 x i32> %a, %b
   %ia = extractelement <16 x i1> %cmp_res, i32 4
-  %ib = extractelement <16 x i1> %cmp_res, i32 12
-
   br i1 %ia, label %A, label %B
-
   A:
     ret <16 x i32>%b
   B:
    %c = add <16 x i32>%b, %a
-  br i1 %ib, label %C, label %D
-  C:
-   %c1 = sub <16 x i32>%c, %a
-   ret <16 x i32>%c1
-  D:
-   %c2 = mul <16 x i32>%c, %a
-   ret <16 x i32>%c2
+   ret <16 x i32>%c
 }
diff --git a/llvm/test/CodeGen/X86/avx512-select.ll b/llvm/test/CodeGen/X86/avx512-select.ll
index d2d6681fb42..83f46984781 100644
--- a/llvm/test/CodeGen/X86/avx512-select.ll
+++ b/llvm/test/CodeGen/X86/avx512-select.ll
@@ -20,3 +20,22 @@ define <8 x i64> @select01(i32 %a, <8 x i64> %b) nounwind {
   ret <8 x i64> %res
 }
 
+; CHECK-LABEL: @select02
+; CHECK: cmpless %xmm0, %xmm3, %k1
+; CHECK-NEXT: vmovss  %xmm2, {{.*}}%xmm1 {%k1}
+; CHECK: ret
+define float @select02(float %a, float %b, float %c, float %eps) {
+  %cmp = fcmp oge float %a, %eps
+  %cond = select i1 %cmp, float %c, float %b
+  ret float %cond
+}
+
+; CHECK-LABEL: @select03
+; CHECK: cmplesd %xmm0, %xmm3, %k1
+; CHECK-NEXT: vmovsd  %xmm2, {{.*}}%xmm1 {%k1}
+; CHECK: ret
+define double @select03(double %a, double %b, double %c, double %eps) {
+  %cmp = fcmp oge double %a, %eps
+  %cond = select i1 %cmp, double %c, double %b
+  ret double %cond
+}
diff --git a/llvm/test/CodeGen/X86/isint.ll b/llvm/test/CodeGen/X86/isint.ll
index 4a98e63f38f..ce3f1357848 100644
--- a/llvm/test/CodeGen/X86/isint.ll
+++ b/llvm/test/CodeGen/X86/isint.ll
@@ -8,8 +8,8 @@ define i32 @isint_return(double %d) nounwind {
   %e = sitofp i32 %i to double
 ; CHECK: cmpeqsd
   %c = fcmp oeq double %d, %e
-; CHECK-NEXT: movd
-; CHECK-NEXT: andl
+; CHECK-NEXT: movq
+; CHECK-NEXT: andq
   %z = zext i1 %c to i32
   ret i32 %z
 }
-- 
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