From 42f7712e2340e64173d53900cf5b84f956af8cf3 Mon Sep 17 00:00:00 2001 From: Andrea Di Biagio Date: Thu, 16 Feb 2017 18:25:37 +0000 Subject: x86 interrupt calling convention: only save xmm registers if the target supports SSE The existing code always saves the xmm registers for 64-bit targets even if the target doesn't support SSE (which is common for kernels). Thus, the compiler inserts movaps instructions which lead to CPU exceptions when an interrupt handler is invoked. This commit fixes this bug by returning a register set without xmm registers from getCalleeSavedRegs and getCallPreservedMask for such targets. Patch by Philipp Oppermann. Differential Revision: https://reviews.llvm.org/D29959 llvm-svn: 295347 --- llvm/test/CodeGen/X86/x86-64-intrcc-nosse.ll | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 llvm/test/CodeGen/X86/x86-64-intrcc-nosse.ll (limited to 'llvm/test') diff --git a/llvm/test/CodeGen/X86/x86-64-intrcc-nosse.ll b/llvm/test/CodeGen/X86/x86-64-intrcc-nosse.ll new file mode 100644 index 00000000000..0bb4e47adf0 --- /dev/null +++ b/llvm/test/CodeGen/X86/x86-64-intrcc-nosse.ll @@ -0,0 +1,19 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=-sse < %s | FileCheck %s + +%struct.interrupt_frame = type { i64, i64, i64, i64, i64 } + +@llvm.used = appending global [1 x i8*] [i8* bitcast (void (%struct.interrupt_frame*, i64)* @test_isr_sse_clobbers to i8*)], section "llvm.metadata" + +; Clobbered SSE must not be saved when the target doesn't support SSE +define x86_intrcc void @test_isr_sse_clobbers(%struct.interrupt_frame* %frame, i64 %ecode) { + ; CHECK-LABEL: test_isr_sse_clobbers: + ; CHECK: # BB#0: + ; CHECK-NEXT: cld + ; CHECK-NEXT: #APP + ; CHECK-NEXT: #NO_APP + ; CHECK-NEXT: addq $8, %rsp + ; CHECK-NEXT: iretq + call void asm sideeffect "", "~{xmm0},~{xmm6}"() + ret void +} -- cgit v1.2.3