From 3be1db82b6cc285994e395fe91588eb8efb81aae Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@intel.com>
Date: Sat, 9 Sep 2017 17:11:59 +0000
Subject: [X86] Don't disable slow INC/DEC if optimizing for size

Summary:
Just because INC/DEC is a little slow on some processors doesn't mean we shouldn't prefer it when optimizing for size.

This appears to match gcc behavior.

Reviewers: chandlerc, zvi, RKSimon, spatel

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D37177

llvm-svn: 312866
---
 llvm/test/CodeGen/X86/slow-incdec.ll | 32 ++++++++++----------------------
 1 file changed, 10 insertions(+), 22 deletions(-)

(limited to 'llvm/test')

diff --git a/llvm/test/CodeGen/X86/slow-incdec.ll b/llvm/test/CodeGen/X86/slow-incdec.ll
index 715a6fe150e..5c406c77aa8 100644
--- a/llvm/test/CodeGen/X86/slow-incdec.ll
+++ b/llvm/test/CodeGen/X86/slow-incdec.ll
@@ -35,33 +35,21 @@ define i32 @dec(i32 %x) {
 }
 
 define i32 @inc_size(i32 %x) optsize {
-; INCDEC-LABEL: inc_size:
-; INCDEC:       # BB#0:
-; INCDEC-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; INCDEC-NEXT:    incl %eax
-; INCDEC-NEXT:    retl
-;
-; ADD-LABEL: inc_size:
-; ADD:       # BB#0:
-; ADD-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; ADD-NEXT:    addl $1, %eax
-; ADD-NEXT:    retl
+; CHECK-LABEL: inc_size:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    incl %eax
+; CHECK-NEXT:    retl
   %r = add i32 %x, 1
   ret i32 %r
 }
 
 define i32 @dec_size(i32 %x) optsize {
-; INCDEC-LABEL: dec_size:
-; INCDEC:       # BB#0:
-; INCDEC-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; INCDEC-NEXT:    decl %eax
-; INCDEC-NEXT:    retl
-;
-; ADD-LABEL: dec_size:
-; ADD:       # BB#0:
-; ADD-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; ADD-NEXT:    addl $-1, %eax
-; ADD-NEXT:    retl
+; CHECK-LABEL: dec_size:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    decl %eax
+; CHECK-NEXT:    retl
   %r = add i32 %x, -1
   ret i32 %r
 }
-- 
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