From 2146a0a90ea227530db7ec89d537f48a8967d038 Mon Sep 17 00:00:00 2001 From: Artem Tamazov Date: Thu, 22 Sep 2016 11:47:21 +0000 Subject: [AMDGPU][mc] Add support for absolute expressions in DPP modifiers. Also added range checking for DPP attributes. Assembler tests added as well. Differential Revision: https://reviews.llvm.org/D24755 llvm-svn: 282145 --- llvm/test/MC/AMDGPU/vop_dpp_expr.s | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 llvm/test/MC/AMDGPU/vop_dpp_expr.s (limited to 'llvm/test') diff --git a/llvm/test/MC/AMDGPU/vop_dpp_expr.s b/llvm/test/MC/AMDGPU/vop_dpp_expr.s new file mode 100644 index 00000000000..0ae74647727 --- /dev/null +++ b/llvm/test/MC/AMDGPU/vop_dpp_expr.s @@ -0,0 +1,35 @@ +// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=CIVI --check-prefix=VI + +zero = 0 +two = 2 +one = 1 + +v_mov_b32 v0, v0 quad_perm:[0+zero,zero-2+two*two,1/one,1] +// VI: v_mov_b32_dpp v0, v0 quad_perm:[0,2,1,1] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x58,0x00,0xff] + +v_mov_b32 v0, v0 row_shl:two-1 +// VI: v_mov_b32_dpp v0, v0 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x01,0xff] + +v_mov_b32 v0, v0 row_shr:0xe+one +// VI: v_mov_b32_dpp v0, v0 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x1f,0x01,0xff] + +v_mov_b32 v0, v0 row_ror:0x6*two +// VI: v_mov_b32_dpp v0, v0 row_ror:12 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x2c,0x01,0xff] + +v_mov_b32 v0, v0 wave_shl:two/2 +// VI: v_mov_b32_dpp v0, v0 wave_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x30,0x01,0xff] + +v_mov_b32 v0, v0 wave_rol:two-one +// VI: v_mov_b32_dpp v0, v0 wave_rol:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x34,0x01,0xff] + +v_mov_b32 v0, v0 wave_shr:1+zero +// VI: v_mov_b32_dpp v0, v0 wave_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x38,0x01,0xff] + +v_mov_b32 v0, v0 wave_ror:two*2-3 +// VI: v_mov_b32_dpp v0, v0 wave_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x3c,0x01,0xff] + +v_mov_b32 v0, v0 row_bcast:150/(two*2+zero/one+two*3) +// VI: v_mov_b32_dpp v0, v0 row_bcast:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x42,0x01,0xff] + +v_mov_b32 v0, v0 quad_perm:[one,two+one,zero,2-one] row_mask:2*5 bank_mask:0x2-one bound_ctrl:1-1 +// VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xa1] -- cgit v1.2.3