From 0112123eea5f36ecc8880632f70d80b6522518d0 Mon Sep 17 00:00:00 2001
From: Marcello Maggioni <hayarms@gmail.com>
Date: Thu, 10 Oct 2019 21:46:26 +0000
Subject: [GISel] Allow getConstantVRegVal() to return G_FCONSTANT values.

In GISel we have both G_CONSTANT and G_FCONSTANT, but because
in GISel we don't really have a concept of Float vs Int value
the only difference between the two is where the data originates
from.

What both G_CONSTANT and G_FCONSTANT return is just a bag of bits
with the constant representation in it.

By making getConstantVRegVal() return G_FCONSTANTs bit representation
as well we allow ConstantFold and other things to operate with
G_FCONSTANT.

Adding tests that show ConstantFolding to work on mixed G_CONSTANT
and G_FCONSTANT sources.

Differential Revision: https://reviews.llvm.org/D68739

llvm-svn: 374458
---
 .../CodeGen/AMDGPU/GlobalISel/legalize-frint.mir   | 36 +++++++++-------------
 1 file changed, 14 insertions(+), 22 deletions(-)

(limited to 'llvm/test')

diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-frint.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-frint.mir
index 5ca81b17b5c..f7b6d1cdb59 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-frint.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-frint.mir
@@ -56,18 +56,14 @@ body: |
 
     ; SI-LABEL: name: test_frint_s64
     ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
-    ; SI: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
-    ; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
-    ; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
-    ; SI: [[AND:%[0-9]+]]:_(s64) = G_AND [[C]], [[C2]]
-    ; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[C]], [[C1]]
-    ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND1]]
-    ; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[OR]]
-    ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[OR]]
+    ; SI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4841369599423283200
+    ; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
+    ; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[COPY1]]
+    ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
     ; SI: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[FADD]], [[FNEG]]
-    ; SI: [[C3:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x432FFFFFFFFFFFFF
+    ; SI: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x432FFFFFFFFFFFFF
     ; SI: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[COPY]]
-    ; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s64), [[C3]]
+    ; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s64), [[C1]]
     ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[COPY]], [[FADD1]]
     ; SI: [[FRINT:%[0-9]+]]:_(s64) = G_FRINT [[COPY]]
     ; SI: $vgpr0_vgpr1 = COPY [[FRINT]](s64)
@@ -131,26 +127,22 @@ body: |
     ; SI-LABEL: name: test_frint_v2s64
     ; SI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
     ; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
-    ; SI: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
-    ; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
-    ; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
-    ; SI: [[AND:%[0-9]+]]:_(s64) = G_AND [[C]], [[C2]]
-    ; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[C]], [[C1]]
-    ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND1]]
-    ; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY [[OR]](s64)
+    ; SI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4841369599423283200
+    ; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
     ; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[UV]], [[COPY1]]
     ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
     ; SI: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[FADD]], [[FNEG]]
-    ; SI: [[C3:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x432FFFFFFFFFFFFF
+    ; SI: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x432FFFFFFFFFFFFF
     ; SI: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[UV]]
-    ; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s64), [[C3]]
+    ; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s64), [[C1]]
     ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[UV]], [[FADD1]]
     ; SI: [[FRINT:%[0-9]+]]:_(s64) = G_FRINT [[UV]]
-    ; SI: [[FADD2:%[0-9]+]]:_(s64) = G_FADD [[UV1]], [[OR]]
-    ; SI: [[FNEG1:%[0-9]+]]:_(s64) = G_FNEG [[OR]]
+    ; SI: [[COPY2:%[0-9]+]]:_(s64) = COPY [[C]](s64)
+    ; SI: [[FADD2:%[0-9]+]]:_(s64) = G_FADD [[UV1]], [[COPY2]]
+    ; SI: [[FNEG1:%[0-9]+]]:_(s64) = G_FNEG [[COPY2]]
     ; SI: [[FADD3:%[0-9]+]]:_(s64) = G_FADD [[FADD2]], [[FNEG1]]
     ; SI: [[FABS1:%[0-9]+]]:_(s64) = G_FABS [[UV1]]
-    ; SI: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS1]](s64), [[C3]]
+    ; SI: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS1]](s64), [[C1]]
     ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP1]](s1), [[UV1]], [[FADD3]]
     ; SI: [[FRINT1:%[0-9]+]]:_(s64) = G_FRINT [[UV1]]
     ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FRINT]](s64), [[FRINT1]](s64)
-- 
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