From a152903c1be57b863e2d6f3050564f4ec2602a26 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@intel.com>
Date: Sun, 20 Aug 2017 21:38:28 +0000
Subject: [InstCombine] Add a test case for a weakness in canEvaluateZExtd. NFC

llvm-svn: 311303
---
 llvm/test/Transforms/InstCombine/cast.ll | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

(limited to 'llvm/test/Transforms')

diff --git a/llvm/test/Transforms/InstCombine/cast.ll b/llvm/test/Transforms/InstCombine/cast.ll
index e852c0ab5af..364337b9693 100644
--- a/llvm/test/Transforms/InstCombine/cast.ll
+++ b/llvm/test/Transforms/InstCombine/cast.ll
@@ -1586,3 +1586,22 @@ define i64 @test94(i32 %a) {
   %4 = sext i8 %3 to i64
   ret i64 %4
 }
+
+; We should be able to remove the zext and trunc here.
+; TODO: This is currently blocked because we don't realize the 'and' has cleared the extra bits that would be shifted in widening the lshr.
+define i32 @test95(i32 %x) {
+; CHECK-LABEL: @test95(
+; CHECK-NEXT:    [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i8
+; CHECK-NEXT:    [[TMP2:%.*]] = lshr i8 [[TMP1]], 6
+; CHECK-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 2
+; CHECK-NEXT:    [[TMP4:%.*]] = or i8 [[TMP3]], 40
+; CHECK-NEXT:    [[TMP5:%.*]] = zext i8 [[TMP4]] to i32
+; CHECK-NEXT:    ret i32 [[TMP5]]
+;
+  %1 = trunc i32 %x to i8
+  %2 = lshr i8 %1, 6
+  %3 = and i8 %2, 2
+  %4 = or i8 %3, 40
+  %5 = zext i8 %4 to i32
+  ret i32 %5
+}
-- 
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