From 220adb63707187abe78542a972b1d427627f99e1 Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Wed, 10 Dec 2014 22:23:07 +0000 Subject: [Hexagon] Adding combine ri/ir instructions. llvm-svn: 223971 --- llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'llvm/test/MC/Disassembler') diff --git a/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt b/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt index d8952102ec7..15977edbd6b 100644 --- a/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt +++ b/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt @@ -10,6 +10,10 @@ # CHECK: r17 = combine(r31.l, r21.l) 0xb0 0xe2 0x0f 0x7c # CHECK: r17:16 = combine(#21, #31) +0xb0 0xe2 0x3f 0x73 +# CHECK: r17:16 = combine(#21, r31) +0xf0 0xe3 0x15 0x73 +# CHECK: r17:16 = combine(r21, #31) 0x10 0xdf 0x15 0xf5 # CHECK: r17:16 = combine(r21, r31) 0xf1 0xc3 0x75 0x73 -- cgit v1.2.3