From 1e1010f56ffd819d2af21fabec7f77c6544cf82f Mon Sep 17 00:00:00 2001 From: Johnny Chen Date: Fri, 1 Apr 2011 22:32:51 +0000 Subject: Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that all the instruction have: let Inst{31-27} = 0b1110; // non-predicated Before, the ARM decoder was confusing: > 0x40 0xf3 0xb8 0x80 as: Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| ------------------------------------------------------------------------------------------------- adcs pc, r8, r0, asr #6 since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'. Now, the AR decoder behaves correctly: > 0x40 0xf3 0xb8 0x80 > END Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| ------------------------------------------------------------------------------------------------- adcshi pc, r8, r0, asr #6 > rdar://problem/9223094 llvm-svn: 128746 --- llvm/test/MC/Disassembler/ARM/arm-tests.txt | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'llvm/test/MC/Disassembler') diff --git a/llvm/test/MC/Disassembler/ARM/arm-tests.txt b/llvm/test/MC/Disassembler/ARM/arm-tests.txt index 4e39e8e9b3c..c66f8ce9688 100644 --- a/llvm/test/MC/Disassembler/ARM/arm-tests.txt +++ b/llvm/test/MC/Disassembler/ARM/arm-tests.txt @@ -226,3 +226,10 @@ # CHECK: blx #60 0x0f 0x00 0x00 0xfa + +# CHECK-NOT: adcs r10, r8, r0, asr #6 +# CHECK: adcshi r10, r8, r0, asr #6 +0x40 0xa3 0xb8 0x80 + +# CHECK: adcshi r10, r8, r0, asr r3 +0x50 0xa3 0xb8 0x80 -- cgit v1.2.3