From d365397daab47927c20be24dce4ddeac8762bcf8 Mon Sep 17 00:00:00 2001 From: Silviu Baranga Date: Thu, 5 Apr 2012 16:13:15 +0000 Subject: Added support for handling unpredictable arithmetic instructions on ARM. llvm-svn: 154100 --- llvm/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt | 12 ------------ llvm/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt | 7 +++++++ 2 files changed, 7 insertions(+), 12 deletions(-) delete mode 100644 llvm/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt create mode 100644 llvm/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt (limited to 'llvm/test/MC/Disassembler/ARM') diff --git a/llvm/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt b/llvm/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt deleted file mode 100644 index 067dcb36a7e..00000000000 --- a/llvm/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt +++ /dev/null @@ -1,12 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} - -# Opcode=0 Name=PHI Format=(42) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 0: 1: 1: 0| 0: 0: 1: 1| 0: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| -# ------------------------------------------------------------------------------------------------- -# -# The bytes have Inst{4} = 1, so it's not an LDRT Encoding A2 instruction. -0x10 0x51 0x37 0xe6 - - diff --git a/llvm/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt b/llvm/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt new file mode 100644 index 00000000000..8ec49cad349 --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt @@ -0,0 +1,7 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s + +# CHECK: warning: potentially undefined +# CHECK: shadd16 r5, r7, r0 +0x10 0x51 0x37 0xe6 + + -- cgit v1.2.3