From 87b7eb9d0f9555835f35350c20d68957c8f1724c Mon Sep 17 00:00:00 2001 From: Adrian Prantl Date: Wed, 1 Oct 2014 18:55:02 +0000 Subject: Move the complex address expression out of DIVariable and into an extra argument of the llvm.dbg.declare/llvm.dbg.value intrinsics. Previously, DIVariable was a variable-length field that has an optional reference to a Metadata array consisting of a variable number of complex address expressions. In the case of OpPiece expressions this is wasting a lot of storage in IR, because when an aggregate type is, e.g., SROA'd into all of its n individual members, the IR will contain n copies of the DIVariable, all alike, only differing in the complex address reference at the end. By making the complex address into an extra argument of the dbg.value/dbg.declare intrinsics, all of the pieces can reference the same variable and the complex address expressions can be uniqued across the CU, too. Down the road, this will allow us to move other flags, such as "indirection" out of the DIVariable, too. The new intrinsics look like this: declare void @llvm.dbg.declare(metadata %storage, metadata %var, metadata %expr) declare void @llvm.dbg.value(metadata %storage, i64 %offset, metadata %var, metadata %expr) This patch adds a new LLVM-local tag to DIExpressions, so we can detect and pretty-print DIExpression metadata nodes. What this patch doesn't do: This patch does not touch the "Indirect" field in DIVariable; but moving that into the expression would be a natural next step. http://reviews.llvm.org/D4919 rdar://problem/17994491 Thanks to dblaikie and dexonsmith for reviewing this patch! Note: I accidentally committed a bogus older version of this patch previously. llvm-svn: 218787 --- llvm/test/DebugInfo/X86/sret.ll | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) (limited to 'llvm/test/DebugInfo/X86/sret.ll') diff --git a/llvm/test/DebugInfo/X86/sret.ll b/llvm/test/DebugInfo/X86/sret.ll index be425de90e2..af219caae5e 100644 --- a/llvm/test/DebugInfo/X86/sret.ll +++ b/llvm/test/DebugInfo/X86/sret.ll @@ -23,9 +23,9 @@ entry: %this.addr = alloca %class.A*, align 8 %i.addr = alloca i32, align 4 store %class.A* %this, %class.A** %this.addr, align 8 - call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !67), !dbg !69 + call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !67, metadata !{i32 786690}), !dbg !69 store i32 %i, i32* %i.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !70), !dbg !71 + call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !70, metadata !{i32 786690}), !dbg !71 %this1 = load %class.A** %this.addr %0 = bitcast %class.A* %this1 to i8***, !dbg !72 store i8** getelementptr inbounds ([4 x i8*]* @_ZTV1A, i64 0, i64 2), i8*** %0, !dbg !72 @@ -36,7 +36,7 @@ entry: } ; Function Attrs: nounwind readnone -declare void @llvm.dbg.declare(metadata, metadata) #1 +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 ; Function Attrs: nounwind uwtable define void @_ZN1AC2ERKS_(%class.A* %this, %class.A* %rhs) unnamed_addr #0 align 2 { @@ -44,9 +44,9 @@ entry: %this.addr = alloca %class.A*, align 8 %rhs.addr = alloca %class.A*, align 8 store %class.A* %this, %class.A** %this.addr, align 8 - call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !74), !dbg !75 + call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !74, metadata !{i32 786690}), !dbg !75 store %class.A* %rhs, %class.A** %rhs.addr, align 8 - call void @llvm.dbg.declare(metadata !{%class.A** %rhs.addr}, metadata !76), !dbg !77 + call void @llvm.dbg.declare(metadata !{%class.A** %rhs.addr}, metadata !76, metadata !{i32 786690}), !dbg !77 %this1 = load %class.A** %this.addr %0 = bitcast %class.A* %this1 to i8***, !dbg !78 store i8** getelementptr inbounds ([4 x i8*]* @_ZTV1A, i64 0, i64 2), i8*** %0, !dbg !78 @@ -64,9 +64,9 @@ entry: %this.addr = alloca %class.A*, align 8 %rhs.addr = alloca %class.A*, align 8 store %class.A* %this, %class.A** %this.addr, align 8 - call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !80), !dbg !81 + call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !80, metadata !{i32 786690}), !dbg !81 store %class.A* %rhs, %class.A** %rhs.addr, align 8 - call void @llvm.dbg.declare(metadata !{%class.A** %rhs.addr}, metadata !82), !dbg !83 + call void @llvm.dbg.declare(metadata !{%class.A** %rhs.addr}, metadata !82, metadata !{i32 786690}), !dbg !83 %this1 = load %class.A** %this.addr %0 = load %class.A** %rhs.addr, align 8, !dbg !84 %m_int = getelementptr inbounds %class.A* %0, i32 0, i32 1, !dbg !84 @@ -81,7 +81,7 @@ define i32 @_ZN1A7get_intEv(%class.A* %this) #0 align 2 { entry: %this.addr = alloca %class.A*, align 8 store %class.A* %this, %class.A** %this.addr, align 8 - call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !86), !dbg !87 + call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !86, metadata !{i32 786690}), !dbg !87 %this1 = load %class.A** %this.addr %m_int = getelementptr inbounds %class.A* %this1, i32 0, i32 1, !dbg !88 %0 = load i32* %m_int, align 4, !dbg !88 @@ -95,10 +95,10 @@ entry: %nrvo = alloca i1 %cleanup.dest.slot = alloca i32 store %class.B* %this, %class.B** %this.addr, align 8 - call void @llvm.dbg.declare(metadata !{%class.B** %this.addr}, metadata !89), !dbg !91 + call void @llvm.dbg.declare(metadata !{%class.B** %this.addr}, metadata !89, metadata !{i32 786690}), !dbg !91 %this1 = load %class.B** %this.addr store i1 false, i1* %nrvo, !dbg !92 - call void @llvm.dbg.declare(metadata !{%class.A* %agg.result}, metadata !93), !dbg !92 + call void @llvm.dbg.declare(metadata !{%class.A* %agg.result}, metadata !93, metadata !{i32 786690}), !dbg !92 call void @_ZN1AC1Ei(%class.A* %agg.result, i32 12), !dbg !92 store i1 true, i1* %nrvo, !dbg !94 store i32 1, i32* %cleanup.dest.slot @@ -118,7 +118,7 @@ define linkonce_odr void @_ZN1AD2Ev(%class.A* %this) unnamed_addr #0 align 2 { entry: %this.addr = alloca %class.A*, align 8 store %class.A* %this, %class.A** %this.addr, align 8 - call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !101), !dbg !102 + call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !101, metadata !{i32 786690}), !dbg !102 %this1 = load %class.A** %this.addr ret void, !dbg !103 } @@ -138,12 +138,12 @@ entry: %cleanup.dest.slot = alloca i32 store i32 0, i32* %retval store i32 %argc, i32* %argc.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32* %argc.addr}, metadata !104), !dbg !105 + call void @llvm.dbg.declare(metadata !{i32* %argc.addr}, metadata !104, metadata !{i32 786690}), !dbg !105 store i8** %argv, i8*** %argv.addr, align 8 - call void @llvm.dbg.declare(metadata !{i8*** %argv.addr}, metadata !106), !dbg !105 - call void @llvm.dbg.declare(metadata !{%class.B* %b}, metadata !107), !dbg !108 + call void @llvm.dbg.declare(metadata !{i8*** %argv.addr}, metadata !106, metadata !{i32 786690}), !dbg !105 + call void @llvm.dbg.declare(metadata !{%class.B* %b}, metadata !107, metadata !{i32 786690}), !dbg !108 call void @_ZN1BC2Ev(%class.B* %b), !dbg !108 - call void @llvm.dbg.declare(metadata !{i32* %return_val}, metadata !109), !dbg !110 + call void @llvm.dbg.declare(metadata !{i32* %return_val}, metadata !109, metadata !{i32 786690}), !dbg !110 call void @_ZN1B9AInstanceEv(%class.A* sret %temp.lvalue, %class.B* %b), !dbg !110 %call = invoke i32 @_ZN1A7get_intEv(%class.A* %temp.lvalue) to label %invoke.cont unwind label %lpad, !dbg !110 @@ -151,7 +151,7 @@ entry: invoke.cont: ; preds = %entry call void @_ZN1AD2Ev(%class.A* %temp.lvalue), !dbg !111 store i32 %call, i32* %return_val, align 4, !dbg !111 - call void @llvm.dbg.declare(metadata !{%class.A* %a}, metadata !113), !dbg !114 + call void @llvm.dbg.declare(metadata !{%class.A* %a}, metadata !113, metadata !{i32 786690}), !dbg !114 call void @_ZN1B9AInstanceEv(%class.A* sret %a, %class.B* %b), !dbg !114 %0 = load i32* %return_val, align 4, !dbg !115 store i32 %0, i32* %retval, !dbg !115 @@ -193,7 +193,7 @@ define linkonce_odr void @_ZN1BC2Ev(%class.B* %this) unnamed_addr #0 align 2 { entry: %this.addr = alloca %class.B*, align 8 store %class.B* %this, %class.B** %this.addr, align 8 - call void @llvm.dbg.declare(metadata !{%class.B** %this.addr}, metadata !123), !dbg !124 + call void @llvm.dbg.declare(metadata !{%class.B** %this.addr}, metadata !123, metadata !{i32 786690}), !dbg !124 %this1 = load %class.B** %this.addr ret void, !dbg !125 } @@ -218,7 +218,7 @@ entry: %exn.slot = alloca i8* %ehselector.slot = alloca i32 store %class.A* %this, %class.A** %this.addr, align 8 - call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !126), !dbg !127 + call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !126, metadata !{i32 786690}), !dbg !127 %this1 = load %class.A** %this.addr invoke void @_ZN1AD2Ev(%class.A* %this1) to label %invoke.cont unwind label %lpad, !dbg !128 -- cgit v1.2.3