From c5cae0f20c946f1842544c7ffbf24659b3c81afc Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Thu, 24 Oct 2013 08:28:24 +0000 Subject: [AArch64] Fix NZCV reg live-in bug in F128CSEL codegen. When generating the IfTrue basic block during the F128CSEL pseudo-instruction handling, the NZCV live-in for the newly created BB wasn't being added. This caused a fault during MI-sched/live range calculation when the predecessor for the fall-through BB didn't have a live-in for phys-reg as expected. llvm-svn: 193316 --- llvm/test/CodeGen/AArch64/regress-fp128-livein.ll | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 llvm/test/CodeGen/AArch64/regress-fp128-livein.ll (limited to 'llvm/test/CodeGen') diff --git a/llvm/test/CodeGen/AArch64/regress-fp128-livein.ll b/llvm/test/CodeGen/AArch64/regress-fp128-livein.ll new file mode 100644 index 00000000000..cb8432a7e4e --- /dev/null +++ b/llvm/test/CodeGen/AArch64/regress-fp128-livein.ll @@ -0,0 +1,17 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s + +; Regression test for NZCV reg live-in not being added to fp128csel IfTrue BB, +; causing a crash during live range calc. +define void @fp128_livein(i64 %a) { + %tobool = icmp ne i64 %a, 0 + %conv = zext i1 %tobool to i32 + %conv2 = sitofp i32 %conv to fp128 + %conv6 = sitofp i32 %conv to double + %call3 = tail call i32 @g(fp128 %conv2) + %call8 = tail call i32 @h(double %conv6) + ret void +} + +declare i32 @f() +declare i32 @g(fp128) +declare i32 @h(double) -- cgit v1.2.3