From 75d1de903f8a88d8b571ba44f764fff349dce381 Mon Sep 17 00:00:00 2001 From: Valery Pykhtin Date: Thu, 26 Jan 2017 10:51:47 +0000 Subject: [AMDGPU] Fix typo in GCNSchedStrategy Differential revision: https://reviews.llvm.org/D28980 llvm-svn: 293171 --- llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) (limited to 'llvm/test/CodeGen') diff --git a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll index e4f6e72e697..ca1b27e7cbc 100644 --- a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll +++ b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll @@ -4,16 +4,11 @@ ; If spilling to smem, additional registers are used for the resource ; descriptor. -; ALL-LABEL: {{^}}max_12_sgprs: +; ALL-LABEL: {{^}}max_9_sgprs: -; FIXME: Should be ablo to skip this copying of the private segment -; buffer because all the SGPR spills are to VGPRs. - -; ALL: s_mov_b64 s[10:11], s[2:3] -; ALL: s_mov_b64 s[8:9], s[0:1] ; ALL: SGPRBlocks: 1 -; ALL: NumSGPRsForWavesPerEU: 14 -define void @max_12_sgprs(i32 addrspace(1)* %out1, +; ALL: NumSGPRsForWavesPerEU: 9 +define void @max_9_sgprs(i32 addrspace(1)* %out1, i32 addrspace(1)* %out2, i32 addrspace(1)* %out3, -- cgit v1.2.3