From 641cb203b6f1ea2d92d17a99a04c8d971f2103e5 Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha <ahmed.bougacha@gmail.com>
Date: Mon, 27 Mar 2017 16:35:31 +0000
Subject: [GlobalISel][AArch64] Select CBZ.

CBZ/CBNZ represent a substantial portion of all conditional branches.
Look through G_ICMP to select them.

We can't use tablegen yet because the existing patterns match an
AArch64ISD node.

llvm-svn: 298856
---
 .../test/CodeGen/AArch64/GlobalISel/select-cbz.mir | 108 +++++++++++++++++++++
 1 file changed, 108 insertions(+)
 create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir

(limited to 'llvm/test/CodeGen')

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
new file mode 100644
index 00000000000..2decb994b96
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
@@ -0,0 +1,108 @@
+# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+  define void @cbz_s32() { ret void }
+  define void @cbz_s64() { ret void }
+  define void @cbnz_s32() { ret void }
+  define void @cbnz_s64() { ret void }
+...
+
+---
+# CHECK-LABEL: name: cbz_s32
+name:            cbz_s32
+legalized:       true
+regBankSelected: true
+
+# CHECK:  body:
+# CHECK:   bb.0:
+# CHECK:    %0 = COPY %w0
+# CHECK:    CBZW %0, %bb.1
+# CHECK:    B %bb.0
+body:             |
+  bb.0:
+    liveins: %w0
+    successors: %bb.0, %bb.1
+
+    %0:gpr(s32) = COPY %w0
+    %1:gpr(s32) = G_CONSTANT i32 0
+    %2:gpr(s1) = G_ICMP intpred(eq), %0, %1
+    G_BRCOND %2(s1), %bb.1
+    G_BR %bb.0
+
+  bb.1:
+...
+
+---
+# CHECK-LABEL: name: cbz_s64
+name:            cbz_s64
+legalized:       true
+regBankSelected: true
+
+# CHECK:  body:
+# CHECK:   bb.0:
+# CHECK:    %0 = COPY %x0
+# CHECK:    CBZX %0, %bb.1
+# CHECK:    B %bb.0
+body:             |
+  bb.0:
+    liveins: %x0
+    successors: %bb.0, %bb.1
+
+    %0:gpr(s64) = COPY %x0
+    %1:gpr(s64) = G_CONSTANT i64 0
+    %2:gpr(s1) = G_ICMP intpred(eq), %0, %1
+    G_BRCOND %2(s1), %bb.1
+    G_BR %bb.0
+
+  bb.1:
+...
+
+---
+# CHECK-LABEL: name: cbnz_s32
+name:            cbnz_s32
+legalized:       true
+regBankSelected: true
+
+# CHECK:  body:
+# CHECK:   bb.0:
+# CHECK:    %0 = COPY %w0
+# CHECK:    CBNZW %0, %bb.1
+# CHECK:    B %bb.0
+body:             |
+  bb.0:
+    liveins: %w0
+    successors: %bb.0, %bb.1
+
+    %0:gpr(s32) = COPY %w0
+    %1:gpr(s32) = G_CONSTANT i32 0
+    %2:gpr(s1) = G_ICMP intpred(ne), %0, %1
+    G_BRCOND %2(s1), %bb.1
+    G_BR %bb.0
+
+  bb.1:
+...
+
+---
+# CHECK-LABEL: name: cbnz_s64
+name:            cbnz_s64
+legalized:       true
+regBankSelected: true
+
+# CHECK:  body:
+# CHECK:   bb.0:
+# CHECK:    %0 = COPY %x0
+# CHECK:    CBNZX %0, %bb.1
+# CHECK:    B %bb.0
+body:             |
+  bb.0:
+    liveins: %x0
+    successors: %bb.0, %bb.1
+
+    %0:gpr(s64) = COPY %x0
+    %1:gpr(s64) = G_CONSTANT i64 0
+    %2:gpr(s1) = G_ICMP intpred(ne), %0, %1
+    G_BRCOND %2(s1), %bb.1
+    G_BR %bb.0
+
+  bb.1:
+...
-- 
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