From 639545b4d8aa3609346fdde711e6918bab129df2 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek <kparzysz@codeaurora.org>
Date: Fri, 19 Aug 2016 16:57:05 +0000
Subject: [Hexagon] Enforce LLSC packetization rules

Ensure that load locked and store conditional instructions are only
packetized with ALU32 instructions.

Patch by Ben Craig.

llvm-svn: 279272
---
 llvm/test/CodeGen/Hexagon/intrinsics/llsc_bundling.ll | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 llvm/test/CodeGen/Hexagon/intrinsics/llsc_bundling.ll

(limited to 'llvm/test/CodeGen')

diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/llsc_bundling.ll b/llvm/test/CodeGen/Hexagon/intrinsics/llsc_bundling.ll
new file mode 100644
index 00000000000..966945b66f4
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/intrinsics/llsc_bundling.ll
@@ -0,0 +1,12 @@
+; RUN: llc -march=hexagon < %s
+target triple = "hexagon-unknown--elf"
+
+; Function Attrs: norecurse nounwind
+define void @_Z4lockv() #0 {
+entry:
+  %__shared_owners = alloca i32, align 4
+  %0 = cmpxchg weak i32* %__shared_owners, i32 0, i32 1 seq_cst seq_cst
+  ret void
+}
+
+attributes #0 = { nounwind }
-- 
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