From 4d026b89da363d55ae46891265c83d616dbfb39e Mon Sep 17 00:00:00 2001
From: Alex Lorenz <arphaman@gmail.com>
Date: Wed, 8 Jul 2015 23:58:31 +0000
Subject: MIR Serialization: Serialize the 'undef' register machine operand
 flag.

llvm-svn: 241762
---
 llvm/test/CodeGen/MIR/X86/undef-register-flag.mir | 42 +++++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 llvm/test/CodeGen/MIR/X86/undef-register-flag.mir

(limited to 'llvm/test/CodeGen')

diff --git a/llvm/test/CodeGen/MIR/X86/undef-register-flag.mir b/llvm/test/CodeGen/MIR/X86/undef-register-flag.mir
new file mode 100644
index 00000000000..83b9e10a80d
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/X86/undef-register-flag.mir
@@ -0,0 +1,42 @@
+# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s
+# This test ensures that the MIR parser parses the 'undef' register flags
+# correctly.
+
+--- |
+
+  define i32 @compute(i32 %a) #0 {
+  body:
+    %c = mul i32 %a, 11
+    ret i32 %c
+  }
+
+  define i32 @foo(i32 %a) #0 {
+  entry:
+    %b = call i32 @compute(i32 %a)
+    ret i32 %b
+  }
+
+  attributes #0 = { "no-frame-pointer-elim"="false" }
+
+...
+---
+name:            compute
+body:
+  - id:          0
+    name:        body
+    instructions:
+      - '%eax = IMUL32rri8 %edi, 11, implicit-def %eflags'
+      - 'RETQ %eax'
+...
+---
+name:            foo
+body:
+  - id:          0
+    name:        entry
+    instructions:
+      # CHECK: - 'PUSH64r undef %rax
+      - 'PUSH64r undef %rax, implicit-def %rsp, implicit %rsp'
+      - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'
+      - '%rdx = POP64r implicit-def %rsp, implicit %rsp'
+      - 'RETQ %eax'
+...
-- 
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