From 49199465a3b21d86a871cb3d368b223c726f8aff Mon Sep 17 00:00:00 2001
From: Cullen Rhodes <cullen.rhodes@arm.com>
Date: Thu, 12 Dec 2019 15:24:30 +0000
Subject: [AArch64][SVE] Implement ptrue intrinsic

Reviewers: sdesmalen, eli.friedman, dancgr, mgudim, cameron.mcinally,
huntergr, efriedma

Reviewed By: sdesmalen

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl,
llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71457
---
 .../AArch64/sve-intrinsics-pred-creation.ll        | 42 ++++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 llvm/test/CodeGen/AArch64/sve-intrinsics-pred-creation.ll

(limited to 'llvm/test/CodeGen')

diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-pred-creation.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-pred-creation.ll
new file mode 100644
index 00000000000..b7131d31918
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-pred-creation.ll
@@ -0,0 +1,42 @@
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+
+;
+; PTRUE
+;
+
+define <vscale x 16 x i1> @ptrue_b8() {
+; CHECK-LABEL: ptrue_b8:
+; CHECK: ptrue p0.b, pow2
+; CHECK-NEXT: ret
+  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 0)
+  ret <vscale x 16 x i1> %out
+}
+
+define <vscale x 8 x i1> @ptrue_b16() {
+; CHECK-LABEL: ptrue_b16:
+; CHECK: ptrue p0.h, vl1
+; CHECK-NEXT: ret
+  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 1)
+  ret <vscale x 8 x i1> %out
+}
+
+define <vscale x 4 x i1> @ptrue_b32() {
+; CHECK-LABEL: ptrue_b32:
+; CHECK: ptrue p0.s, mul3
+; CHECK-NEXT: ret
+  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 30)
+  ret <vscale x 4 x i1> %out
+}
+
+define <vscale x 2 x i1> @ptrue_b64() {
+; CHECK-LABEL: ptrue_b64:
+; CHECK: ptrue p0.d
+; CHECK-NEXT: ret
+  %out = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
+  ret <vscale x 2 x i1> %out
+}
+
+declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 %pattern)
+declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 %pattern)
+declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 %pattern)
+declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 %pattern)
-- 
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