From 3a68eb150b66ede806db279995b28050ca60b34b Mon Sep 17 00:00:00 2001
From: Richard Osborne <richard@xmos.com>
Date: Tue, 15 Mar 2011 13:45:47 +0000
Subject: Add XCore intrinsics for getps, setps, setsr and clrsr.

llvm-svn: 127678
---
 llvm/test/CodeGen/XCore/ps-intrinsics.ll | 18 ++++++++++++++++++
 llvm/test/CodeGen/XCore/sr-intrinsics.ll | 18 ++++++++++++++++++
 2 files changed, 36 insertions(+)
 create mode 100644 llvm/test/CodeGen/XCore/ps-intrinsics.ll
 create mode 100644 llvm/test/CodeGen/XCore/sr-intrinsics.ll

(limited to 'llvm/test/CodeGen')

diff --git a/llvm/test/CodeGen/XCore/ps-intrinsics.ll b/llvm/test/CodeGen/XCore/ps-intrinsics.ll
new file mode 100644
index 00000000000..92b26c75e0e
--- /dev/null
+++ b/llvm/test/CodeGen/XCore/ps-intrinsics.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=xcore | FileCheck %s
+declare i32 @llvm.xcore.getps(i32)
+declare void @llvm.xcore.setps(i32, i32)
+
+define i32 @getps(i32 %reg) nounwind {
+; CHECK: getps:
+; CHECK: get r0, ps[r0]
+	%result = call i32 @llvm.xcore.getps(i32 %reg)
+	ret i32 %result
+}
+
+
+define void @setps(i32 %reg, i32 %value) nounwind {
+; CHECK: setps:
+; CHECK: set ps[r0], r1
+	call void @llvm.xcore.setps(i32 %reg, i32 %value)
+	ret void
+}
diff --git a/llvm/test/CodeGen/XCore/sr-intrinsics.ll b/llvm/test/CodeGen/XCore/sr-intrinsics.ll
new file mode 100644
index 00000000000..e12ed038030
--- /dev/null
+++ b/llvm/test/CodeGen/XCore/sr-intrinsics.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=xcore | FileCheck %s
+declare void @llvm.xcore.setsr(i32)
+declare void @llvm.xcore.clrsr(i32)
+
+define void @setsr() nounwind {
+; CHECK: setsr:
+; CHECK: setsr 128
+	call void @llvm.xcore.setsr(i32 128)
+	ret void
+}
+
+
+define void @clrsr() nounwind {
+; CHECK: clrsr:
+; CHECK: clrsr 128
+	call void @llvm.xcore.clrsr(i32 128)
+	ret void
+}
-- 
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