From 33caeadd90ac7217f1d0bbf43dac68cd38e7dae7 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 5 Sep 2017 17:33:58 +0000 Subject: [AVX512] Remove patterns for (v8f32 (X86vzmovl (insert_subvector undef, (v4f32 (scalar_to_vector FR32X:)), (iPTR 0)))) and the same for v4f64. We don't have this same pattern for AVX2 so I don't believe we should have it for AVX512. We also didn't have it for v16f32. llvm-svn: 312543 --- llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll | 1 + 1 file changed, 1 insertion(+) (limited to 'llvm/test/CodeGen') diff --git a/llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll b/llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll index 92afa063e3c..26a866c20ac 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll @@ -1277,6 +1277,7 @@ define <4 x double> @insert_reg_and_zero_v4f64(double %a) { ; ; AVX512VL-LABEL: insert_reg_and_zero_v4f64: ; AVX512VL: # BB#0: +; AVX512VL-NEXT: # kill: %XMM0 %XMM0 %YMM0 ; AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX512VL-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1] ; AVX512VL-NEXT: retq -- cgit v1.2.3