From 04b16b51ec2903f1be8a4f9297a24e73b0bbda52 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Tue, 23 Dec 2014 08:38:50 +0000 Subject: [PowerPC] Don't attempt a 64-bit pow2 division on PPC32 In r224033, in moving the signed power-of-2 division expansion into BuildSDIVPow2, I accidentally made it possible to attempt the lowering for a 64-bit division on PPC32. This later asserts. Fixes PR21928. llvm-svn: 224758 --- llvm/test/CodeGen/PowerPC/sdiv-pow2.ll | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'llvm/test/CodeGen') diff --git a/llvm/test/CodeGen/PowerPC/sdiv-pow2.ll b/llvm/test/CodeGen/PowerPC/sdiv-pow2.ll index c6330a6807a..5ec019dfb4a 100644 --- a/llvm/test/CodeGen/PowerPC/sdiv-pow2.ll +++ b/llvm/test/CodeGen/PowerPC/sdiv-pow2.ll @@ -1,4 +1,5 @@ ; RUN: llc -mcpu=ppc64 < %s | FileCheck %s +; RUN: llc -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc < %s | FileCheck -check-prefix=CHECK-32 %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -25,6 +26,10 @@ entry: ; CHECK: sradi [[REG1:[0-9]+]], 3, 3 ; CHECK: addze 3, [[REG1]] ; CHECK: blr + +; CHECK-32-LABEL @foo8 +; CHECK-32-NOT: sradi +; CHECK-32: blr } ; Function Attrs: nounwind readnone @@ -52,6 +57,10 @@ entry: ; CHECK: addze [[REG2:[0-9]+]], [[REG1]] ; CHECK: neg 3, [[REG2]] ; CHECK: blr + +; CHECK-32-LABEL @foo8n +; CHECK-32-NOT: sradi +; CHECK-32: blr } attributes #0 = { nounwind readnone } -- cgit v1.2.3