From a5b9645c4b7a1d8be5e41081b99f27b49b8aa8cf Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Thu, 4 Jun 2009 22:49:04 +0000 Subject: Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897 --- llvm/test/CodeGen/X86/vec_ss_load_fold.ll | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'llvm/test/CodeGen/X86/vec_ss_load_fold.ll') diff --git a/llvm/test/CodeGen/X86/vec_ss_load_fold.ll b/llvm/test/CodeGen/X86/vec_ss_load_fold.ll index 0f15f923fea..69900a686e2 100644 --- a/llvm/test/CodeGen/X86/vec_ss_load_fold.ll +++ b/llvm/test/CodeGen/X86/vec_ss_load_fold.ll @@ -20,8 +20,8 @@ define i16 @test1(float %f) nounwind { } define i16 @test2(float %f) nounwind { - %tmp28 = sub float %f, 1.000000e+00 ; [#uses=1] - %tmp37 = mul float %tmp28, 5.000000e-01 ; [#uses=1] + %tmp28 = fsub float %f, 1.000000e+00 ; [#uses=1] + %tmp37 = fmul float %tmp28, 5.000000e-01 ; [#uses=1] %tmp375 = insertelement <4 x float> undef, float %tmp37, i32 0 ; <<4 x float>> [#uses=1] %tmp48 = tail call <4 x float> @llvm.x86.sse.min.ss( <4 x float> %tmp375, <4 x float> < float 6.553500e+04, float undef, float undef, float undef > ) ; <<4 x float>> [#uses=1] %tmp59 = tail call <4 x float> @llvm.x86.sse.max.ss( <4 x float> %tmp48, <4 x float> < float 0.000000e+00, float undef, float undef, float undef > ) ; <<4 x float>> [#uses=1] -- cgit v1.2.3