From a79ac14fa68297f9888bc70a10df5ed9b8864e38 Mon Sep 17 00:00:00 2001
From: David Blaikie <dblaikie@gmail.com>
Date: Fri, 27 Feb 2015 21:17:42 +0000
Subject: [opaque pointer type] Add textual IR support for explicit type
 parameter to load instruction

Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

llvm-svn: 230794
---
 llvm/test/CodeGen/X86/pointer-vector.ll | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

(limited to 'llvm/test/CodeGen/X86/pointer-vector.ll')

diff --git a/llvm/test/CodeGen/X86/pointer-vector.ll b/llvm/test/CodeGen/X86/pointer-vector.ll
index 5e0c2dae083..48c8b2376bd 100644
--- a/llvm/test/CodeGen/X86/pointer-vector.ll
+++ b/llvm/test/CodeGen/X86/pointer-vector.ll
@@ -31,7 +31,7 @@ entry:
 ;CHECK: LOAD0
 define <4 x i8*> @LOAD0(<4 x i8*>* %p) nounwind {
 entry:
-  %G = load <4 x i8*>* %p
+  %G = load <4 x i8*>, <4 x i8*>* %p
 ;CHECK: movaps
   ret <4 x i8*> %G
 ;CHECK: ret
@@ -40,7 +40,7 @@ entry:
 ;CHECK: LOAD1
 define <4 x i8*> @LOAD1(<4 x i8*>* %p) nounwind {
 entry:
-  %G = load <4 x i8*>* %p
+  %G = load <4 x i8*>, <4 x i8*>* %p
 ;CHECK: movdqa
 ;CHECK: pshufd
 ;CHECK: movdqa
@@ -55,11 +55,11 @@ define <4 x i8*> @LOAD2(<4 x i8*>* %p) nounwind {
 entry:
   %I = alloca <4 x i8*>
 ;CHECK: sub
-  %G = load <4 x i8*>* %p
+  %G = load <4 x i8*>, <4 x i8*>* %p
 ;CHECK: movaps
   store <4 x i8*> %G, <4 x i8*>* %I
 ;CHECK: movaps
-  %Z = load <4 x i8*>* %I
+  %Z = load <4 x i8*>, <4 x i8*>* %I
   ret <4 x i8*> %Z
 ;CHECK: add
 ;CHECK: ret
@@ -68,7 +68,7 @@ entry:
 ;CHECK: INT2PTR0
 define <4 x i32> @INT2PTR0(<4 x i8*>* %p) nounwind {
 entry:
-  %G = load <4 x i8*>* %p
+  %G = load <4 x i8*>, <4 x i8*>* %p
 ;CHECK: movl
 ;CHECK: movaps
   %K = ptrtoint <4 x i8*> %G to <4 x i32>
@@ -79,7 +79,7 @@ entry:
 ;CHECK: INT2PTR1
 define <4 x i32*> @INT2PTR1(<4 x i8>* %p) nounwind {
 entry:
-  %G = load <4 x i8>* %p
+  %G = load <4 x i8>, <4 x i8>* %p
 ;CHECK: movl
 ;CHECK: pmovzxbd (%
   %K = inttoptr <4 x i8> %G to <4 x i32*>
@@ -90,7 +90,7 @@ entry:
 ;CHECK: BITCAST0
 define <4 x i32*> @BITCAST0(<4 x i8*>* %p) nounwind {
 entry:
-  %G = load <4 x i8*>* %p
+  %G = load <4 x i8*>, <4 x i8*>* %p
 ;CHECK: movl
   %T = bitcast <4 x i8*> %G to <4 x i32*>
 ;CHECK: movaps
@@ -101,7 +101,7 @@ entry:
 ;CHECK: BITCAST1
 define <2 x i32*> @BITCAST1(<2 x i8*>* %p) nounwind {
 entry:
-  %G = load <2 x i8*>* %p
+  %G = load <2 x i8*>, <2 x i8*>* %p
 ;CHECK: movl
 ;CHECK: pmovzxdq
   %T = bitcast <2 x i8*> %G to <2 x i32*>
@@ -112,8 +112,8 @@ entry:
 ;CHECK: ICMP0
 define <4 x i32> @ICMP0(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind {
 entry:
-  %g0 = load <4 x i8*>* %p0
-  %g1 = load <4 x i8*>* %p1
+  %g0 = load <4 x i8*>, <4 x i8*>* %p0
+  %g1 = load <4 x i8*>, <4 x i8*>* %p1
   %k = icmp sgt <4 x i8*> %g0, %g1
   ;CHECK: pcmpgtd
   %j = select <4 x i1> %k, <4 x i32> <i32 0, i32 1, i32 2, i32 4>, <4 x i32> <i32 9, i32 8, i32 7, i32 6>
@@ -124,8 +124,8 @@ entry:
 ;CHECK: ICMP1
 define <4 x i32> @ICMP1(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind {
 entry:
-  %g0 = load <4 x i8*>* %p0
-  %g1 = load <4 x i8*>* %p1
+  %g0 = load <4 x i8*>, <4 x i8*>* %p0
+  %g1 = load <4 x i8*>, <4 x i8*>* %p1
   %k = icmp eq <4 x i8*> %g0, %g1
   ;CHECK: pcmpeqd
   %j = select <4 x i1> %k, <4 x i32> <i32 0, i32 1, i32 2, i32 4>, <4 x i32> <i32 9, i32 8, i32 7, i32 6>
-- 
cgit v1.2.3