From 8cc938807381dc507b8b86b54384518cab5d8d67 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@gmail.com>
Date: Thu, 13 Oct 2011 07:09:14 +0000
Subject: Add X86 TZCNT instruction and patterns to select it. Also added
 core-avx2 processor which is gcc's name for Haswell.

llvm-svn: 141854
---
 llvm/test/CodeGen/X86/bmi.ll | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 llvm/test/CodeGen/X86/bmi.ll

(limited to 'llvm/test/CodeGen/X86/bmi.ll')

diff --git a/llvm/test/CodeGen/X86/bmi.ll b/llvm/test/CodeGen/X86/bmi.ll
new file mode 100644
index 00000000000..8817e224984
--- /dev/null
+++ b/llvm/test/CodeGen/X86/bmi.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s -march=x86-64 -mattr=+bmi | FileCheck %s
+
+define i32 @t1(i32 %x) nounwind  {
+	%tmp = tail call i32 @llvm.cttz.i32( i32 %x )
+	ret i32 %tmp
+; CHECK: t1:
+; CHECK: tzcntl
+}
+
+declare i32 @llvm.cttz.i32(i32) nounwind readnone
+
+define i16 @t2(i16 %x) nounwind  {
+	%tmp = tail call i16 @llvm.cttz.i16( i16 %x )
+	ret i16 %tmp
+; CHECK: t2:
+; CHECK: tzcntw
+}
+
+declare i16 @llvm.cttz.i16(i16) nounwind readnone
+
+define i64 @t3(i64 %x) nounwind  {
+	%tmp = tail call i64 @llvm.cttz.i64( i64 %x )
+	ret i64 %tmp
+; CHECK: t3:
+; CHECK: tzcntq
+}
+
+declare i64 @llvm.cttz.i64(i64) nounwind readnone
+
+define i8 @t4(i8 %x) nounwind  {
+	%tmp = tail call i8 @llvm.cttz.i8( i8 %x )
+	ret i8 %tmp
+; CHECK: t4:
+; CHECK: tzcntw
+}
+
+declare i8 @llvm.cttz.i8(i8) nounwind readnone
+
-- 
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