From 1a87fcb9ba5189dc1702140eb3e152d6aa1d66e5 Mon Sep 17 00:00:00 2001
From: Bruno Cardoso Lopes <bruno.cardoso@gmail.com>
Date: Wed, 17 Aug 2011 22:12:20 +0000
Subject: Fix PR10688. Add support for spliting 256-bit vector shifts when the
 shift amount is variable

llvm-svn: 137885
---
 llvm/test/CodeGen/X86/avx-shift.ll | 11 +++++++++++
 1 file changed, 11 insertions(+)

(limited to 'llvm/test/CodeGen/X86/avx-shift.ll')

diff --git a/llvm/test/CodeGen/X86/avx-shift.ll b/llvm/test/CodeGen/X86/avx-shift.ll
index 791194fc1c7..3ea39a2358e 100644
--- a/llvm/test/CodeGen/X86/avx-shift.ll
+++ b/llvm/test/CodeGen/X86/avx-shift.ll
@@ -62,3 +62,14 @@ define <16 x i16> @vshift07(<16 x i16> %a) nounwind readnone {
   ret <16 x i16> %s
 }
 
+;;; Support variable shifts
+; CHECK: _vshift08
+; CHECK: vextractf128 $1
+; CHECK: vpslld $23
+; CHECK: vextractf128 $1
+; CHECK: vpslld $23
+define <8 x i32> @vshift08(<8 x i32> %a) nounwind {
+  %bitop = shl <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, %a
+  ret <8 x i32> %bitop
+}
+
-- 
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