From 325c9c5e84ae6f0b0856bfb00d6278a2fdbfd969 Mon Sep 17 00:00:00 2001
From: Thomas Lively <tlively@google.com>
Date: Thu, 25 Oct 2018 01:46:07 +0000
Subject: [WebAssembly] Set LoadExt and TruncStore actions for SIMD types

Summary: Fixes part of the problem reported in bug 39275.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits, alexcrichton

Differential Revision: https://reviews.llvm.org/D53542

llvm-svn: 345230
---
 .../WebAssembly/simd-ext-load-trunc-store.ll       | 60 ++++++++++++++++++++++
 1 file changed, 60 insertions(+)
 create mode 100644 llvm/test/CodeGen/WebAssembly/simd-ext-load-trunc-store.ll

(limited to 'llvm/test/CodeGen/WebAssembly')

diff --git a/llvm/test/CodeGen/WebAssembly/simd-ext-load-trunc-store.ll b/llvm/test/CodeGen/WebAssembly/simd-ext-load-trunc-store.ll
new file mode 100644
index 00000000000..f128483cb9a
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/simd-ext-load-trunc-store.ll
@@ -0,0 +1,60 @@
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s
+
+; Check that store in memory with smaller lanes are loaded and stored
+; as expected. This is a regression test for part of bug 39275.
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
+target triple = "wasm32-unknown-unknown"
+
+; CHECK-LABEL: load_ext_2xi32:
+; CHECK-NEXT: .param i32{{$}}
+; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: i64.load32_u $push[[L0:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: i64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]]{{$}}
+; CHECK-NEXT: i64.load32_u $push[[L2:[0-9]+]]=, 4($0){{$}}
+; CHECK-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L1]], 1, $pop[[L2]]{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+define <2 x i32> @load_ext_2xi32(<2 x i32>* %p) {
+  %1 = load <2 x i32>, <2 x i32>* %p, align 4
+  ret <2 x i32> %1
+}
+
+; CHECK-LABEL: load_zext_2xi32:
+; CHECK-NEXT: .param i32{{$}}
+; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: i64.load32_u $push[[L0:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: i64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]]{{$}}
+; CHECK-NEXT: i64.load32_u $push[[L2:[0-9]+]]=, 4($0){{$}}
+; CHECK-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L1]], 1, $pop[[L2]]{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_zext_2xi32(<2 x i32>* %p) {
+  %1 = load <2 x i32>, <2 x i32>* %p, align 4
+  %2 = zext <2 x i32> %1 to <2 x i64>
+  ret <2 x i64> %2
+}
+
+; CHECK-LABEL: load_sext_2xi32:
+; CHECK-NEXT: .param i32{{$}}
+; CHECK-NEXT: .result v128{{$}}
+; CHECK-NEXT: i64.load32_s $push[[L0:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: i64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]]{{$}}
+; CHECK-NEXT: i64.load32_s $push[[L2:[0-9]+]]=, 4($0){{$}}
+; CHECK-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L1]], 1, $pop[[L2]]{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_sext_2xi32(<2 x i32>* %p) {
+  %1 = load <2 x i32>, <2 x i32>* %p, align 4
+  %2 = sext <2 x i32> %1 to <2 x i64>
+  ret <2 x i64> %2
+}
+
+; CHECK-LABEL: store_trunc_2xi32:
+; CHECK-NEXT: .param i32, v128{{$}}
+; CHECK-NEXT: i64x2.extract_lane $push[[L0:[0-9]+]]=, $1, 1
+; CHECK-NEXT: i64.store32 4($0), $pop[[L0]]
+; CHECK-NEXT: i64x2.extract_lane $push[[L1:[0-9]+]]=, $1, 0
+; CHECK-NEXT: i64.store32 0($0), $pop[[L1]]
+; CHECK-NEXT: return
+define void @store_trunc_2xi32(<2 x i32>* %p, <2 x i32> %x) {
+  store <2 x i32> %x, <2 x i32>* %p, align 4
+  ret void
+}
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