From be0afb087055d5c23f0406e7219e3d7ded108d36 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei@ca.ibm.com>
Date: Mon, 26 Mar 2018 17:46:25 +0000
Subject: [Power9]Legalize and emit code for quad-precision convert from
 double-precision

Legalize and emit code for quad-precision floating point operation xscvdpqp
and add option to guard the quad precision operation support.

Differential Revision: https://reviews.llvm.org/D44746

llvm-svn: 328558
---
 llvm/test/CodeGen/PowerPC/f128-arith.ll | 30 +++++++++++++++++++++++++++++-
 1 file changed, 29 insertions(+), 1 deletion(-)

(limited to 'llvm/test/CodeGen/PowerPC')

diff --git a/llvm/test/CodeGen/PowerPC/f128-arith.ll b/llvm/test/CodeGen/PowerPC/f128-arith.ll
index 3fa5566d9ea..857e6d5e641 100644
--- a/llvm/test/CodeGen/PowerPC/f128-arith.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-arith.ll
@@ -1,4 +1,5 @@
-; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -enable-ppc-quad-precision < %s | FileCheck %s
 
 ; Function Attrs: norecurse nounwind
 define void @qpAdd(fp128* nocapture readonly %a, fp128* nocapture %res) {
@@ -147,3 +148,30 @@ entry:
 ; CHECK: stxv
 ; CHECK: blr
 }
+
+; Function Attrs: norecurse nounwind
+define void @dpConv2qp(double* nocapture readonly %a, fp128* nocapture %res) {
+entry:
+  %0 = load double, double* %a, align 8
+  %conv = fpext double %0 to fp128
+  store fp128 %conv, fp128* %res, align 16
+  ret void
+; CHECK-LABEL: dpConv2qp
+; CHECK-NOT: bl __extenddftf2
+; CHECK: lxsd
+; CHECK: xscvdpqp
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @dpConv2qp_02(double %a, fp128* nocapture %res) {
+entry:
+  %conv = fpext double %a to fp128
+  store fp128 %conv, fp128* %res, align 16
+  ret void
+; CHECK-LABEL: dpConv2qp_02
+; CHECK-NOT: bl __extenddftf2
+; CHECK: xxlor
+; CHECK: xscvdpqp
+; CHECK: blr
+}
-- 
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