From 84aafee4fbf3e7bd47b9b1accc8f45cfa337fc03 Mon Sep 17 00:00:00 2001 From: Hiroshi Inoue Date: Tue, 27 Jun 2017 12:43:08 +0000 Subject: [SelectionDAG] set dereferenceable flag in MergeConsecutiveStores to fix assetion failure When SelectionDAG merges consecutive stores and loads in MergeConsecutiveStores, it does not set dereferenceable flag for a created load instruction. This results in an assertion failure if SelectionDAG commonizes this load instruction with other load instructions, as well as it may miss optimization opportunities. This patch sat dereferenceable flag for the newly created load instruction if all the load instructions to be merged are dereferenceable. Differential Revision: https://reviews.llvm.org/D34679 llvm-svn: 306404 --- .../PowerPC/merge_stores_dereferenceable.ll | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 llvm/test/CodeGen/PowerPC/merge_stores_dereferenceable.ll (limited to 'llvm/test/CodeGen/PowerPC') diff --git a/llvm/test/CodeGen/PowerPC/merge_stores_dereferenceable.ll b/llvm/test/CodeGen/PowerPC/merge_stores_dereferenceable.ll new file mode 100644 index 00000000000..29aee7a3825 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/merge_stores_dereferenceable.ll @@ -0,0 +1,24 @@ +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s + +; This code causes an assertion failure if dereferenceable flag is not properly set when in merging consecutive stores +; CHECK-LABEL: func: +; CHECK: lxvd2x [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK-NOT: lxvd2x +; CHECK: stxvd2x [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} + +define <2 x i64> @func(i64* %pdst) { +entry: + %a = alloca [4 x i64], align 8 + %psrc0 = bitcast [4 x i64]* %a to i64* + %psrc1 = getelementptr inbounds i64, i64* %psrc0, i64 1 + %d0 = load i64, i64* %psrc0 + %d1 = load i64, i64* %psrc1 + %pdst0 = getelementptr inbounds i64, i64* %pdst, i64 0 + %pdst1 = getelementptr inbounds i64, i64* %pdst, i64 1 + store i64 %d0, i64* %pdst0, align 8 + store i64 %d1, i64* %pdst1, align 8 + %psrcd = bitcast [4 x i64]* %a to <2 x i64>* + %vec = load <2 x i64>, <2 x i64>* %psrcd + ret <2 x i64> %vec +} + -- cgit v1.2.3