From 33e529d56b2ff4b19357ed2d874fe5bb87f98052 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Mon, 6 Aug 2012 21:21:44 +0000 Subject: MFTB on PPC64 should really be encoded using MFSPR. The MFTB instruction itself is being phased out, and its functionality is provided by MFSPR. According to the ISA docs, using MFSPR works on all known chips except for the 601 (which did not have a timebase register anyway) and the POWER3. Thanks to Adhemerval Zanella for pointing this out! llvm-svn: 161346 --- llvm/test/CodeGen/PowerPC/ppc64-cyclecounter.ll | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'llvm/test/CodeGen/PowerPC') diff --git a/llvm/test/CodeGen/PowerPC/ppc64-cyclecounter.ll b/llvm/test/CodeGen/PowerPC/ppc64-cyclecounter.ll index c1df3c7ec21..38406cabb2d 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-cyclecounter.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-cyclecounter.ll @@ -9,7 +9,7 @@ entry: } ; CHECK: @test1 -; CHECK: mftb +; CHECK: mfspr 3, 268 declare i64 @llvm.readcyclecounter() -- cgit v1.2.3