From 0cfa7b7ad035cd349be419b8601748bfcb1edf1b Mon Sep 17 00:00:00 2001 From: Kit Barton Date: Tue, 3 Mar 2015 19:55:45 +0000 Subject: Add the following 64-bit vector integer arithmetic instructions added in POWER8: vaddudm vsubudm vmulesw vmulosw vmuleuw vmulouw vmuluwm vmaxsd vmaxud vminsd vminud vcmpequd vcmpequd. vcmpgtsd vcmpgtsd. vcmpgtud vcmpgtud. vrld vsld vsrd vsrad Phabricator review: http://reviews.llvm.org/D7959 llvm-svn: 231115 --- llvm/test/CodeGen/PowerPC/vec_minmax.ll | 34 +++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 llvm/test/CodeGen/PowerPC/vec_minmax.ll (limited to 'llvm/test/CodeGen/PowerPC/vec_minmax.ll') diff --git a/llvm/test/CodeGen/PowerPC/vec_minmax.ll b/llvm/test/CodeGen/PowerPC/vec_minmax.ll new file mode 100644 index 00000000000..e9ba6a01a9b --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/vec_minmax.ll @@ -0,0 +1,34 @@ +; Test the vector min/max doubleword instructions added for P8 +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s + +declare <2 x i64> @llvm.ppc.altivec.vmaxsd(<2 x i64>, <2 x i64>) nounwind readnone +declare <2 x i64> @llvm.ppc.altivec.vmaxud(<2 x i64>, <2 x i64>) nounwind readnone +declare <2 x i64> @llvm.ppc.altivec.vminsd(<2 x i64>, <2 x i64>) nounwind readnone +declare <2 x i64> @llvm.ppc.altivec.vminud(<2 x i64>, <2 x i64>) nounwind readnone + +define <2 x i64> @test_vmaxsd(<2 x i64> %x, <2 x i64> %y) { + %tmp = tail call <2 x i64> @llvm.ppc.altivec.vmaxsd(<2 x i64> %x, <2 x i64> %y) + ret <2 x i64> %tmp +; CHECK: vmaxsd 2, 2, 3 +} + +define <2 x i64> @test_vmaxud(<2 x i64> %x, <2 x i64> %y) { + %tmp = tail call <2 x i64> @llvm.ppc.altivec.vmaxud(<2 x i64> %x, <2 x i64> %y) + ret <2 x i64> %tmp +; CHECK: vmaxud 2, 2, 3 +} + +define <2 x i64> @test_vminsd(<2 x i64> %x, <2 x i64> %y) { + %tmp = tail call <2 x i64> @llvm.ppc.altivec.vminsd(<2 x i64> %x, <2 x i64> %y) + ret <2 x i64> %tmp +; CHECK: vminsd 2, 2, 3 +} + +define <2 x i64> @test_vminud(<2 x i64> %x, <2 x i64> %y) { + %tmp = tail call <2 x i64> @llvm.ppc.altivec.vminud(<2 x i64> %x, <2 x i64> %y) + ret <2 x i64> %tmp +; CHECK: vminud 2, 2, 3 +} + + -- cgit v1.2.3