From 5ea0349ef59288bb239036b87bbcfcb41e3f62e8 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Sat, 12 Jan 2013 19:06:44 +0000 Subject: When lowering an inreg sext first shift left, then right arithmetically. Shifting right two times will only yield zero. Should fix SingleSource/UnitTests/SignlessTypes/factor. llvm-svn: 172322 --- llvm/test/CodeGen/PowerPC/vec_extload.ll | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'llvm/test/CodeGen/PowerPC/vec_extload.ll') diff --git a/llvm/test/CodeGen/PowerPC/vec_extload.ll b/llvm/test/CodeGen/PowerPC/vec_extload.ll index 42334d7030d..998645d90da 100644 --- a/llvm/test/CodeGen/PowerPC/vec_extload.ll +++ b/llvm/test/CodeGen/PowerPC/vec_extload.ll @@ -15,7 +15,7 @@ define <16 x i8> @v16si8_sext_in_reg(<16 x i8> %a) { ret <16 x i8> %c } ; CHECK: v16si8_sext_in_reg: -; CHECK: vsrb +; CHECK: vslb ; CHECK: vsrab ; CHECK: blr @@ -37,7 +37,7 @@ define <8 x i16> @v8si16_sext_in_reg(<8 x i16> %a) { ret <8 x i16> %c } ; CHECK: v8si16_sext_in_reg: -; CHECK: vsrh +; CHECK: vslh ; CHECK: vsrah ; CHECK: blr @@ -61,7 +61,7 @@ define <4 x i32> @v4si32_sext_in_reg(<4 x i32> %a) { ret <4 x i32> %c } ; CHECK: v4si32_sext_in_reg: -; CHECK: vsrw +; CHECK: vslw ; CHECK: vsraw ; CHECK: blr -- cgit v1.2.3