From 11b9e452f6ebeabac58c7f16393d9bf1ff0edc65 Mon Sep 17 00:00:00 2001
From: Hal Finkel <hfinkel@anl.gov>
Date: Tue, 6 Aug 2013 17:03:03 +0000
Subject: Add PPC64 mulli pattern

The PPC backend had been missing a pattern to generate mulli for 64-bit
multiples. We had been generating it only for 32-bit multiplies. Unfortunately,
generating li + mulld unnecessarily increases register pressure.

llvm-svn: 187807
---
 llvm/test/CodeGen/PowerPC/mulli64.ll | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 llvm/test/CodeGen/PowerPC/mulli64.ll

(limited to 'llvm/test/CodeGen/PowerPC/mulli64.ll')

diff --git a/llvm/test/CodeGen/PowerPC/mulli64.ll b/llvm/test/CodeGen/PowerPC/mulli64.ll
new file mode 100644
index 00000000000..21bc9cc3770
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/mulli64.ll
@@ -0,0 +1,16 @@
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+define i64 @foo(i64 %a) #0 {
+entry:
+  %mul = mul nsw i64 %a, 3
+  ret i64 %mul
+}
+
+; CHECK-LABEL: @foo
+; CHECK: mulli 3, 3, 3
+; CHECK: blr
+
+attributes #0 = { nounwind readnone }
+
-- 
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