From a79ac14fa68297f9888bc70a10df5ed9b8864e38 Mon Sep 17 00:00:00 2001
From: David Blaikie <dblaikie@gmail.com>
Date: Fri, 27 Feb 2015 21:17:42 +0000
Subject: [opaque pointer type] Add textual IR support for explicit type
 parameter to load instruction

Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

llvm-svn: 230794
---
 llvm/test/CodeGen/PowerPC/inlineasm-i64-reg.ll | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

(limited to 'llvm/test/CodeGen/PowerPC/inlineasm-i64-reg.ll')

diff --git a/llvm/test/CodeGen/PowerPC/inlineasm-i64-reg.ll b/llvm/test/CodeGen/PowerPC/inlineasm-i64-reg.ll
index 4d8e704f07a..05f2a197cd5 100644
--- a/llvm/test/CodeGen/PowerPC/inlineasm-i64-reg.ll
+++ b/llvm/test/CodeGen/PowerPC/inlineasm-i64-reg.ll
@@ -19,18 +19,18 @@ entry:
   store %struct.BG_CoordinateMapping_t* %map, %struct.BG_CoordinateMapping_t** %map.addr, align 8
   store i64* %numentries, i64** %numentries.addr, align 8
   store i64 1055, i64* %r0, align 8
-  %0 = load i64* %mapsize.addr, align 8
+  %0 = load i64, i64* %mapsize.addr, align 8
   store i64 %0, i64* %r3, align 8
-  %1 = load %struct.BG_CoordinateMapping_t** %map.addr, align 8
+  %1 = load %struct.BG_CoordinateMapping_t*, %struct.BG_CoordinateMapping_t** %map.addr, align 8
   %2 = ptrtoint %struct.BG_CoordinateMapping_t* %1 to i64
   store i64 %2, i64* %r4, align 8
-  %3 = load i64** %numentries.addr, align 8
+  %3 = load i64*, i64** %numentries.addr, align 8
   %4 = ptrtoint i64* %3 to i64
   store i64 %4, i64* %r5, align 8
-  %5 = load i64* %r0, align 8
-  %6 = load i64* %r3, align 8
-  %7 = load i64* %r4, align 8
-  %8 = load i64* %r5, align 8
+  %5 = load i64, i64* %r0, align 8
+  %6 = load i64, i64* %r3, align 8
+  %7 = load i64, i64* %r4, align 8
+  %8 = load i64, i64* %r5, align 8
   %9 = call { i64, i64, i64, i64 } asm sideeffect "sc", "={r0},={r3},={r4},={r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 %5, i64 %6, i64 %7, i64 %8) #1, !srcloc !0
 
 ; CHECK-LABEL: @Kernel_RanksToCoords
@@ -52,9 +52,9 @@ entry:
   store i64 %asmresult1, i64* %r3, align 8
   store i64 %asmresult2, i64* %r4, align 8
   store i64 %asmresult3, i64* %r5, align 8
-  %10 = load i64* %r3, align 8
+  %10 = load i64, i64* %r3, align 8
   store i64 %10, i64* %tmp
-  %11 = load i64* %tmp
+  %11 = load i64, i64* %tmp
   %conv = trunc i64 %11 to i32
   ret i32 %conv
 }
@@ -87,7 +87,7 @@ entry:
 
 if.then:                                          ; preds = %entry
   call void @mtrace()
-  %.pre = load i32* %argc.addr, align 4
+  %.pre = load i32, i32* %argc.addr, align 4
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
-- 
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