From 1b1e25b7c51a4f021050cd693f77dc9d4a84740f Mon Sep 17 00:00:00 2001
From: Daniel Sanders <daniel.sanders@imgtec.com>
Date: Fri, 27 Sep 2013 10:08:31 +0000
Subject: [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report
 fatal error when using it in FR=0 mode.

llvm-svn: 191498
---
 llvm/test/CodeGen/Mips/msa/elm_move.ll | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'llvm/test/CodeGen/Mips/msa/elm_move.ll')

diff --git a/llvm/test/CodeGen/Mips/msa/elm_move.ll b/llvm/test/CodeGen/Mips/msa/elm_move.ll
index 2f1763b4f3c..37fde15c3b5 100644
--- a/llvm/test/CodeGen/Mips/msa/elm_move.ll
+++ b/llvm/test/CodeGen/Mips/msa/elm_move.ll
@@ -1,7 +1,7 @@
 ; Test the MSA move intrinsics (which are encoded with the ELM instruction
 ; format).
 
-; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
 
 @llvm_mips_move_vb_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
 @llvm_mips_move_vb_RES  = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
-- 
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