From 2a232d81f6575b18638b30c8fd33b084baa652a8 Mon Sep 17 00:00:00 2001
From: Akira Hatanaka <ahatanaka@mips.com>
Date: Mon, 19 Dec 2011 19:44:09 +0000
Subject: Remove definitions of double word shift plus 32 instructions.
 Assembler or direct-object emitter should emit the appropriate shift
 instruction depending on the shift amount.

llvm-svn: 146893
---
 llvm/test/CodeGen/Mips/mips64ext.ll | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'llvm/test/CodeGen/Mips/mips64ext.ll')

diff --git a/llvm/test/CodeGen/Mips/mips64ext.ll b/llvm/test/CodeGen/Mips/mips64ext.ll
index 33af0d852da..ae6078b829c 100644
--- a/llvm/test/CodeGen/Mips/mips64ext.ll
+++ b/llvm/test/CodeGen/Mips/mips64ext.ll
@@ -3,8 +3,8 @@
 define i64 @zext64_32(i32 %a) nounwind readnone {
 entry:
 ; CHECK: addiu $[[R0:[0-9]+]], ${{[0-9]+}}, 2
-; CHECK: dsll32 $[[R1:[0-9]+]], $[[R0]], 0
-; CHECK: dsrl32  ${{[0-9]+}}, $[[R1]], 0
+; CHECK: dsll $[[R1:[0-9]+]], $[[R0]], 32
+; CHECK: dsrl ${{[0-9]+}}, $[[R1]], 32
   %add = add i32 %a, 2
   %conv = zext i32 %add to i64
   ret i64 %conv
-- 
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